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MM32F103CET Fiches technique(PDF) 75 Page - MindMotion Microelectronics |
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MM32F103CET Fiches technique(HTML) 75 Page - MindMotion Microelectronics |
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75 / 89 page ![]() DS_MM32F103xx_o_Ver1.13 Electrical characteristics EG = Gain error: The deviation between the last ideal transition and the last actual transi- tion. ED = Differential linearity error: The maximum deviation between the actual step and the ideal value. EL = Integral linearity error: The maximum deviation between any actual conversion and the associated line of the endpoint. 439454 12-bit converter VAIN RAIN (1) AINx Parasi c capacitance Cparasi c(2) CADC (1) RADC (1) Sanple and hold ADC converter Figure 25. Typical connection diagram using the ADC 1. See Table 42 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7pF) . A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. PCB design recommendations The power supply must be connected as shown below. The 10nFcapacitor in the figure must be a ceramic capacitor (good quality) , and they should be as close as possible to the MCU chip. www.mm32mcu.com 69/83 |
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