EMC2302 datasheet(17/70 Pages) MICROCHIP

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DS20006532A-page 17

EMC2301/2/3/5

EQUATION 4-3:

SIMPLIFIED TACH

CONVERSION

4.4.2

VALID TACHOMETER READINGS

The Valid TACH Count registers store the maximum

TACH Reading Register value to indicate that each fan

is spinning properly. The value is referenced at the end

of the Spin Up Routine to determine if the fan has

started operating and decide if the device needs to

retry. See Section 4.4.1 “Tachometer Counts to

RPM” for translating the count to an RPM.

If the TACH Reading Register value exceeds the Valid

TACH Count Register (indicating that the Fan RPM is

below the threshold set by this count), then a Stalled

Fan is detected. In this condition, the algorithm will

automatically begin its Spin Up Routine.

If a TACH Target setting is set above the Valid TACH

Count setting, then that setting will be ignored and the

algorithm will use the current fan drive setting. The

Valid Tach Count value is stored in Register 6-19.

4.4.3

STALLED FAN

A stalled fan is detected if the tach counter exceeds the

user-programmable Valid TACH Count setting. If a stall

is detected, the device will flag the fan as stalled and

trigger an interrupt.

If the RPM-based Fan Speed Control algorithm is

enabled, the algorithm will automatically attempt to

restart the fan until it detects a valid tachometer level or

is disabled.

The FNSTL status bit indicates that a stalled fan was

detected (see Register 6-2). This bit is checked

conditionally depending on the mode of operation.

• Whenever the Direct Setting mode or the Spin Up

Routine is enabled, the FNSTL interrupt will be

masked for the duration of the programmed Spin

Up Time (see Table 4-11) to allow the fan to reach

a valid speed without generating unnecessary

interrupts.

• In Direct Setting mode, whenever the TACH

Reading Register value exceeds the Valid TACH

Count Register setting, the FNSTL status bit will

be set.

• When using the RPM-based Fan Speed Control

algorithm, the Stalled Fan condition is checked

whenever the Update Time is met and the fan

drive setting is updated. It is not a continuous

check.

4.4.4

AGING FAN OR INVALID DRIVE

DETECTION

This feature is useful to detect Aging Fan conditions

(where the fan’s natural maximum speed degrades

over time) or a speed setting that is faster than the fan

is capable of. The EMC2301/2/3/5 contains circuitry

that detects if the programmed fan speed can be

reached by the fan.

If the target fan speed cannot be reached within a user

defined band of tach counts at maximum drive stored in

(see Register 6-5) are set and the ALERT pin is

asserted. Table 4-8 shows the decode based on DFC

bits in Register 6-16. This setting determines how long

the aging fan circuitry will interrogate the Tach Reading

4.5

CLK Pin

The CLK pin has multiple functionality as determined

by the pull-up decode of the ADDR_SEL pin and the

settings of the Configuration register. The functionality

associated with the CLK pin upon device power-up is

independent of the CLK pin functionality after the

device has been configured. The added functionality of

the CLK pin is available only on the EMC2303/5.

4.6

Pull-Up Decode

The EMC2303/5 have the ability to program the SMBus

address and default fan setting using a resistor pull-up

on CLK. If additional functionality is enabled via the

ADDR_SEL pin (see Table 5-1), then the CLK pin

should be configured with a pull-up resistor to VDD and

should not be used. The value of the pull-up resistor on

the CLK pin is used to determine the default drive state

of all fan drivers as shown in Table 4-9.

RPM

3932160 m



COUNT

-------------------------------

Where:

COUNT = TACH Reading Register value (in

decimal)

TABLE 4-8:

DRIVE FAIL SAMPLE TIME

DFCX[1:0]

Number of Update Periods

Disabled - the Drive Fail detection

circuitry is disabled (default)

16 - the Drive Fail detection circuitry will

count for 16 update periods

32 - the Drive Fail detection circuitry will

count for 32 update periods

64 - the Drive Fail detection circuitry will

count for 64 update periods

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