EMC2302 datasheet(21/70 Pages) MICROCHIP

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 2021 Microchip Technology Inc.

DS20006532A-page 21

EMC2301/2/3/5

5.0

SYSTEM MANAGEMENT BUS

PROTOCOL

The EMC2301/2/3/5 communicates with a host control-

ler through the SMBus. The SMBus is a two-wire serial

communication protocol between a computer host and

its peripheral devices. A detailed timing diagram is

shown in Figure 5-1. Stretching of the SMCLK signal is

supported; however, the EMC2301/2/3/5 will not

stretch the clock signal.

FIGURE 5-1:

SMBus Timing Diagram.

5.1

SMBus Start Bit

The SMBus Start bit is defined as a transition of the

SMBus Data line from a logic ‘1’ state to a logic ‘0’ state

while the SMBus Clock line is in a logic ‘1’ state.

5.2

SMBus Address and RD/WR Bit

The SMBus Address Byte consists of the 7-bit client

address followed by an RD/WR indicator bit. If this RD/

WR bit is a logic ‘0’, then the SMBus Host is writing

data to the client device. If this RD/WR bit is a logic ‘1’,

then the SMBus Host is reading data from the client

device.

The EMC2303 and EMC2305 will respond to one of

multiple SMBus addresses determined by the pull-up

resistor on the ADDR_SEL pin. The ADDR_SEL pin

decodes one of six pull-up resistors upon device

power-up. Depending on the resistor used, the CLK pin

may also be used to select additional functionality. The

resistor values for each address is shown in Table 5-1.

The EMC2302-1 SMBus address is set at

0101_110(r/w)b.

The EMC2302-2 SMBus address is set at

0101_111(r/w)b.

The EMC2301 SMBus address is set at

0101_111(r/w)b.

SMDATA

SMCLK

TLOW

TRISE

THIGH

TFALL

TBUF

THD:STA

S - Start Condition

P - Stop Condition

THD:DAT

TSU:DAT

TSU:STA

THD:STA

TSU:STO

TABLE 5-1:

ADDR_SEL PIN DECODE

(EMC2303/5 ONLY)

Pull-Up

Resistor

SMBus

Address

Additional

Functions

4.7 k

 ± 5%

0101_110(r/w)

None - CLK pin

used as clock

input or output.

6.8 k

 ± 5%

0101_111(r/w)

10 k

 ± 5%

0101_100(r/w)

15 k

 ± 5%

0101_101(r/w)

22 k

 ± 5%

1001_100(r/w)

33 k

 ± 5%

1001_101(r/w)

CLK pin used to

determine default

fan drive - see

Section 4.6

“Pull-Up

Decode”.

The CLK pin can-

not be used as a

clock input or

output

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