EMC2302 datasheet(39/70 Pages) MICROCHIP

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 2021 Microchip Technology Inc.

DS20006532A-page 39

EMC2301/2/3/5

6.15

Fan Configuration 2 Registers

The Fan Configuration 2 registers control the tachome-

ter measurement and advanced features of the RPM-

based Fan Speed Control algorithm (see Section 4.3

“RPM-Based Fan Speed Control Algorithm”).

bit 4-3

EDGx[1:0]: Edges. Sets the number of edges to sample when calculating RPM, where “x” is 1 to 5,

depending on device features.

11 = 9 edges sampled (4 poles) - effective Tach multiplier is 2, based on two pole fans

10 = 7 edges sampled (3 poles) - effective Tach multiplier is 1.5, based on two pole fans

01 = 5 edges sampled (2 poles) - effective Tach multiplier is 1, based on two pole fans

00 = 3 edges sampled (1 pole) - effective Tach multiplier is 0.5, based on two pole fans

bit 2-0

UDTx[2:0]: Update Time. Sets the PID update rate for closed loop control, where “x” is 1 to 5,

depending on device features. The Update Time, along with the Fan Step register, is used to con-

trol the ramp rate of the drive response to provide a cleaner transition of the actual fan operation

as the desired fan speed changes.

111 = 1600 ms update interval

110 = 1200 ms update interval

101 = 800 ms update interval

100 = 500 ms update interval

011 = 400 ms update interval

010 = 300 ms update interval

001 = 200 ms update interval

000 = 100 ms update interval

Note:

Increasing the number of edges measured with respect to the number of poles of the fan will cause the

TACH Reading registers to indicate a fan speed that is higher or lower than the actual speed. In order for

the FSC algorithm to operate correctly, the TACH Target must be updated by the user to accommodate this

shift. The Effective Tach Multiplier is used as a direct multiplier term that is applied to the Actual RPM to

achieve the Reported RPM. It should only be applied if the number of edges measured does not match the

number of edges expected based on the number of poles of the fan (which is fixed for any given fan).

Contact Microchip for recommended settings when using fans with more or fewer than two poles.

FAN CONFIG - FAN CONFIGURATION REGISTERS

(ADDRESSES 32H, 42H, 52H, 62H, 72H) (CONTINUED)

FAN CONFIG 2 - FAN CONFIGURATION 2 REGISTERS

(ADDRESSES 33H, 43H, 53H, 63H, 73H)

U-0

RW-0

U-0

—

ENRCx

GHENx

DPTx[1:0]

ERGx[1:0]

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented bit, read as ‘0’.

bit 6

ENRCx: Enable Ramp Rate Control, where “x” is 1 to 5, depending on device features. This is

available only when ENAGx = 0.

1 = Ramp Rate Control enabled.

0 = Ramp Rate Control disabled.

bit 5

GHENx: Glitch Filter Enable. Enables the noise filter that removes high-frequency noise injected on

the TACHx pin, where “x” is 1 to 5, depending on device features.

1 = Glitch filter enabled.

0 = Glitch filter disabled.

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