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EMC2302 Fiches technique(PDF) 34 Page - Microchip Technology |
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EMC2302 Fiches technique(HTML) 34 Page - Microchip Technology |
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34 / 70 page ![]() EMC2301/2/3/5 DS20006532A-page 34 2021 Microchip Technology Inc. 6.8 PWM Polarity Configuration Registers The PWM Polarity Configuration registers control the output type and polarity of all PWM outputs. REGISTER 6-7: PWM POLARITY CONFIG - PWM POLARITY CONFIGURATION REGISTER (ADDRESS 2AH) U-0 U-0 U-0 RW-0 RW-0 RW-0 RW-0 RW-0 — — — PLRITY5 PLRITY4 PLRITY3 PLRITY2 PLRITY1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented bits, read as ‘0’. bit 4 PLRITY5: Sets the PWM output polarity 1 = PWM 5 drive setting of 00h produces 100% duty cycle, drive setting of FFh produces 0% duty cycle. 0 = PWM 5 drive setting of 00h produces 0% duty cycle, drive setting of FFh produces 100% duty cycle. bit 3 PLRITY4: Sets the PWM output polarity 1 = PWM 4 drive setting of 00h produces 100% duty cycle, drive setting of FFh produces 0% duty cycle. 0 = PWM 4 drive setting of 00h produces 0% duty cycle, drive setting of FFh produces 100% duty cycle. bit 2 PLRITY3: Sets the PWM output polarity 1 = PWM 3 drive setting of 00h produces 100% duty cycle, drive setting of FFh produces 0% duty cycle. 0 = PWM 3 drive setting of 00h produces 0% duty cycle, drive setting of FFh produces 100% duty cycle. bit 1 PLRITY2: Sets the PWM output polarity 1 = PWM 2 drive setting of 00h produces 100% duty cycle, drive setting of FFh produces 0% duty cycle. 0 = PWM 2 drive setting of 00h produces 0% duty cycle, drive setting of FFh produces 100% duty cycle. bit 0 PLRITY1: Sets the PWM output polarity 1 = PWM 1 drive setting of 00h produces 100% duty cycle, drive setting of FFh produces 0% duty cycle. 0 = PWM 1 drive setting of 00h produces 0% duty cycle, drive setting of FFh produces 100% duty cycle. |
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