PC87413 datasheet(104/257 Pages) NSC

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5.0 X-Bus Extension (Continued)

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104

Revision1.2

Figure 25. Turbo Latched Address Mode - X-Bus Read Access Cycle

Turbo Write Transactions. A Turbo write cycle starts by outputting the lower 12 address signals on address signals

XA11-0 and by outputting address lines 27-20 on data signals XD7-0 on the rising edge of the clock. One CLK cycle later,

a strobe signal (XSTB2) is asserted to latch the address in an external latch. One CLK cycle after that, a second set of ad-

dress lines (19-12) is placed on data pins XD7-0. These can be latched by the strobe signal XSTB1, asserted one cycle later

on the rising edge of the clock. One CLK cycle later, the last group of address lines (11-4) is output on the data signals XD7-

0. The XSTB0, asserted one CLK cycle later on the rising edge of the clock, can be used to latch this part of the address.

One CLK cycle later on the rising edge of the clock, the PC8741x outputs the data signals on data pins XD7-0. At this point,

all the addresses are available either at the address outputs of the PC8741x (XA11-0) or at the outputs of the three latches.

The system may require only part of these addresses, depending on the size of the memory or peripheral address space.

One CLK cycle later, the chip-select signal XCSn is asserted, based on the XCSn Turbo mode setting. From this point, the

write continues as described for the Normal Address Turbo transaction, Mode 0. XSTB2-0 are de-asserted one CLK cycle

after the de-assertion of XCSn. At this time, the latched address becomes invalid. At the same time, the address signals

XA11-0 are driven to low level.

CLK

(Internal; for

XD7-0

XA27-0

XA11-0

XCSn

XWR_XRW

(After Latching)

[27-20]

[19-12]

XRD_XEN

XSTB2

XSTB1

XSTB0

(Availability on Device Pins

Depends on Multiplexing)

Transaction Continues as for Non-Latched, Turbo X-Bus Address Mode 0 Read

[11-4]

Starting point

Reference Only)

PC87413 Fiches technique(PDF) 104 Page - National Semiconductor (TI)