PC87413 datasheet(75/257 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.2

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3.15 X-BUS CONFIGURATION

This section is relevant only for the PC87416 and PC87417.

3.15.1

Logical Device F (X-Bus) Configuration

Table 27 lists the configuration registers that affect the X-Bus functional block. The X-Bus base address registers point to

the X-Bus runtime registers described in Section 5.4 on page 107. The memory space to which the X-Bus responds is de-

fined by the configuration registers described in the sections below. See Section 3.2.3 on page 40 for a detailed description

of the other configuration registers. The standard configuration registers are powered by VDD, however the specific config-

uration registers are powered by VSB.

Table 27. X-Bus Conﬁguration Registers

3.15.2

X-Bus I/O Range Programming

LPC I/O transactions can be forwarded to the X-Bus of the PC8741x device. The X-Bus I/O configuration registers define

the map of I/O addresses to be forwarded. The PC8741x provides five individually enabled I/O zones. Each zone generates

an internal select signal that is sent to the X-Bus functional block. The mapping of the internal select signals to the XCS0-3

signals of the PC8741x device is controlled by the X-Bus functional block. See Section 5.2 on page 92 for further details.

The supported I/O zones are:

User-Deﬁned I/O Zone 0 through 3 (UDIZ0-3) - speciﬁed using the zone size (2n where n is 0 through 8) and start

address (must be aligned with the zone size).

Debug Port Address (TST) - This zone is for debug use only.

Index

Conﬁguration Register or Action

Type

Power Well

Reset

30h

Activate (see Section 3.3.1 on page 43). When bit 0 is cleared, the

registers of this logical device are not accessible.

R/W

VDD

00h

60h

Base Address MSB register.

R/W

VDD

00h

61h

Base Address LSB register. Bits 4-0 (for A4-A0) are read only, 00000b. Varies per bit

VDD

00h

70h

Interrupt Number and wake-up on IRQ enable.

VDD

00h

71h

Interrupt Type.

VDD

00h

74h

Report no DMA assignment.

VDD

04h

75h

Report no DMA assignment.

VDD

04h

F0h

X-Bus I/O Conﬁguration register (XIOCNF).

Varies per bit

VSB

00h

F1h

X-Bus I/O Base Address 1 High Byte register (XIOBA1H).

R/W or RO

VSB

00h

F2h

X-Bus I/O Base Address 1 Low Byte register (XIOBA1L).

R/W or RO

VSB

00h

F3h

X-Bus I/O Size 1 Conﬁguration register (XIOSIZE1).

R/W or RO

VSB

00h

F4h

X-Bus I/O Base Address 2 High Byte register (XIOBA2H).

R/W or RO

VSB

00h

F5h

X-Bus I/O Base Address 2 Low Byte register (XIOBA2L).

R/W or RO

VSB

00h

F6h

X-Bus I/O Size 2 Conﬁguration register (XIOSIZE2).

R/W or RO

VSB

00h

F7h

X-Bus Memory Conﬁguration register 1 (XMEMCNF1).

R/W or RO

VSB

00h

F8h

X-Bus Memory Conﬁguration register 2 (XMEMCNF2).

Varies per bit

VSB

00h

F9h

X-Bus Memory Base Address High Byte register (XMEMBAH).

R/W or RO

VSB

00h

FAh

X-Bus Memory Base Address Low Byte register (XMEMBAL).

R/W or RO

VSB

00h

FBh

X-Bus Memory Size Conﬁguration register (XMEMSIZE).

R/W or RO

VSB

00h

FCh

X-Bus IRQ Mapping register (XIRQMAP).

R/W

VSB

00h

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