PC87413 datasheet(72/257 Pages) NSC

72 / 257 page

3.0 Device Architecture and Configuration (Continued)

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Revision1.2

3.14.3

GPIO Pin Select Register (GPSEL)

This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the

GPIO configuration registers). Since access to the pin configuration requires two transactions (first to GPSEL, then to the

configuration register) and since the LPC bus and ACCESS.bus concurrently access the module (PC87413 and PC87417),

the GPSEL register is duplicated (one GPSEL register is accessed by the host and one by the ACCESS.bus). This register

is reset by hardware to 00h.

Power Well:VSB

Location:Index F0h

Type:

R/W

3.14.4

GPIO Pin Configuration Register 1 (GPCFG1)

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All the GPIO

Pin Configuration registers have a common bit structure, as shown below. Ports 1 and 4 are reset by hardware to

01000X00b. Ports 0, 2, 3, 5 and 6 are reset to 00000X00b (see Table 26 on page 73 for the value of ‘X’).

Power Well:VSB

Location:Index F1h

Type:

Varies per bit

Ports 1 and 4 (With Wake-Up Event Detection Capability)

Ports 0, 2, 3, 5 and 6 (Without Wake-Up Event Detection Capability)

Bit

76543210

Name

Reserved

PORTSEL

Reserved

PINSEL

Reset

00000000

Bit

Description

Reserved.

5-4

PORTSEL (Port Select). These bits select the GPIO port to be configured:

000: Port 0 (default)

001 to 110: Binary value of port numbers 1-6, respectively (all other values are reserved)

Reserved.

2-0

PINSEL (Pin Select). These bits select the GPIO pin of the selected port, to be conﬁgured:

000:

Pin 0 (default)

001 to 111:

Binary value of pin number 1-7, respectively

Bit

76543210

Name

Reserved

EVDBNC

EVPOL

EVTYPE

LOCKCFP

PUPCTL

OUTTYPE

OUTENA

Reset

01000

see Table 26

Bit

76543210

Name

Reserved

LOCKCFP

PUPCTL

OUTTYPE

OUTENA

Reset

00000

see Table 26

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