PC87413 datasheet(23/257 Pages) NSC

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1.0 Signal/Pin Connection and Description (Continued)

Revision 1.2

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1.4.1

LPC Interface

1.4.2

ACCESS.bus (ACB) Interface (PC87413 and PC87417)

1.4.3

X-Bus Extension (PC87416 and PC87417)

Signal

Pin(s)

I/O Buffer Type Power Well

Description

LAD3-01

1. This pin is neither 5-Volt tolerant, nor back-drive protected.

110-113 I/O

INPCI/OPCI

VDD

LPC Address-Data. Multiplexed command, address bidirectional

data and cycle status.

LCLK1

114

INPCI

VDD

LPC Clock. Derived from the PCI clock (up to 33 MHz).

LFRAME1

117

INPCI

VDD

LPC Frame. Low pulse indicates the beginning of a new LPC cy-

cle or termination of a broken cycle.

LDRQ1

118

OPCI

VDD

LPC DMA Request. Encoded DMA request for LPC Interface.

LRESET1

120

INPCI

VDD

LPC Reset. Derived from the PCI system reset.

SERIRQ1

119

I/O

INPCI/OPCI

VDD

Serial IRQ. The interrupt requests are serialized over a single pin,

where each IRQ level is delivered during a designated time slot.

CLKRUN1

124

I/OD INPCI/OD6

VDD

Clock Run. Indicates that LCLK is going to be stopped and re-

quests full-speed LCLK (same behavior as PCI CLKRUN).

Signal

Pin(s)

I/O Buffer Type Power Well

Description

ACBCLK

I/O

INSM/OD6

VSB

ACCESS.bus Clock. An internal pull-up for this pin is optional.

ACBDAT

I/O

INSM/OD6

VSB

ACCESS.bus Serial Data. An internal pull-up for this pin is

optional.

Signal

Pin/s

I/O Buffer Type Power Well

Description

XRD_XEN

O3/6

VSB

Read. Active (low) level indicates read cycle on the X-Bus.

Enable. Active (high) level indicates valid data on the X-Bus.

XWR_XRW15

O3/6

VSB

Write. Active (low) level indicates a write cycle on the X-Bus.

Read/Write. A high level indicates a read cycle on the X-Bus; a

low level indicates a write cycle on the X-Bus.

XD7-0

24-31

I/O

INTS/O3/6

VSB

Data Bus. 8-bit data multiplexed with the address lines XA27-4.

XA11-4,

XA3-0

1-8

16-19

OO3/6

VSB

Address Bus. The XA27-12 address lines are always multiplexed

with the data lines.

XSTB2-0

32-34

O3/6

VSB

Address Strobes. Control the strobe of up to three external

latches for the multiplexed address lines.

XCS3-0

20-23

O3/6

VSB

Chip Selects. Control the selection of up to four devices residing

on the X-Bus.

XRDY

INTS

VSB

I/O Ready. Instructs the PC8741x to extend the access cycle.

XIRQ

INTS

VSB

X-Bus Interrupt. Converted into serial interrupt by the Interrupt

Serializer. The system conﬁguration includes the interrupt number

associated with this signal.

PC87413 Fiches technique(PDF) 23 Page - National Semiconductor (TI)

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