PC87413 datasheet(69/257 Pages) NSC

69 / 257 page

3.0 Device Architecture and Configuration (Continued)

Revision 1.2

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3.13.3

KBC Configuration Register

This register is reset by hardware to 40h.

Power Well:VDD

Location:Index F0h

Type:

R/W

Usage Hints:

1. To change the clock frequency of the KBC:

a. Disable the KBC logical devices.

b. Change the frequency setting.

c. Enable the KBC logical devices.

2. Before swapping between the Keyboard and Mouse Interface pins, disable the KBC logical devices and both pin sets.

After swapping, the software must issue a synchronization command to the Keyboard and Mouse through the KBC to

regain synchronization with these devices.

Bit

76543210

Name

KBC Clock Source

Reserved

Swap

Reserved

TRI-STATE

Control

Reset

01000000

Required

Bit

Description

7-6

KBC Clock Source. The clock source can be changed only when the KBC is inactive (disabled).

Bits

7 6

Source

0 0:

8 MHz

0 1:

12 MHz (default)

1 0:

16 MHz

1 1:

Reserved

5-4

Reserved.

Swap. This bit swaps between the Keyboard and Mouse Interface pins.

0: KBCLK and KBDAT are Keyboard Interface; MCLK and MDAT are Mouse Interface (default)

1: KBCLK and KBDAT are Mouse Interface; MCLK and MDAT are Keyboard Interface

2-1

Reserved.

TRI-STATE Control. If the keyboard is inactive (see Section 3.3.1 on page 43) when this bit is set, the KBD pins

(KBCLK and KBDAT) are in TRI-STATE. If the mouse is inactive (see Section 3.3.1 on page 43) when this bit is set,

the mouse pins (MCLK and MDAT) are in TRI-STATE.

0: Disabled (default)

1: Enabled

PC87413 Fiches technique(PDF) 69 Page - National Semiconductor (TI)

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