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PC87413 Fiches technique(PDF) 60 Page - National Semiconductor (TI) |
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PC87413 Fiches technique(HTML) 60 Page - National Semiconductor (TI) |
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60 / 257 page ![]() 3.0 Device Architecture and Configuration (Continued) www.national.com 60 Revision1.2 3.8.4 Drive ID Register This register is reset by hardware to 00h. This register controls bits 5 and 4 of the TDR register in Enhanced mode. Power Well:VDD Location:Index F1h Type: R/W Usage Hints: Some BIOS implementations support automatic media sense FDDs, in which case bit 5 of the TDR register in the Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support automatic media sense, bits 1 and/or 3 of the Drive ID register must be set to 1 (to indicate non-valid media sense). When Drive 0 or Drive 1 is selected, the Drive ID bit is reflected on bit 5 of the TDR register in Enhanced mode. Bit 76543210 Name Reserved Drive 1 ID Drive 0 ID Reset 00000000 Bit Description 7-4 Reserved. 3-2 Drive 1 ID. When drive 1 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively. 1-0 Drive 0 ID. When drive 0 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively. |
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