PC87413 datasheet(67/257 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.2

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3.12 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION

3.12.1

General Description

System Wake-up Control provides wake-up and power management functionality according to ACPI specification (see Sec-

tion 9.1 on page 161). Its registers are VPP or VSB powered.

3.12.2

Logical Device 4 (SWC) Configuration

Table 21 lists the configuration registers that affect the SWC. See Section 3.2.3 on page 40 for a detailed description of

these registers. All these registers are VDD powered.

Table 21. System Wake-Up Control (SWC) Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Power Well

Reset

30h

Activate. When bit 0 is cleared, the runtime registers of this logical device are

not accessible (see Section 3.3.1 on page 43).1

1. The logical device runtime registers are maintained and all wake-up detection mechanisms are functional.

R/W

VDD

00h

60h

SWC Base Address MSB register.

R/W

VDD

00h

61h

SWC Base Address LSB register. Bits 4-0 (for A4-0) are read only, 00000b.

R/W

VDD

00h

62h

PM1b_EVT_BLK Base Address MSB register.

R/W

VDD

00h

63h

PM1b_EVT_BLK Base Address LSB register. Bits 1-0 (for A1-0) are read only,

00b.

R/W

VDD

00h

64h

PM1b_CNT_BLK Base Address MSB register.

R/W

VDD

00h

65h

PM1b_CNT_BLK Base Address LSB register. Bits 1-0 (for A1-0) are read only,

00b.

R/W

VDD

00h

66h

GPE1_BLK Base Address MSB register.

R/W

VDD

00h

67h

GPE1_BLK Base Address LSB register. Bits 2-0 (for A2-0) are read only, 000b.

R/W

VDD

00h

70h

Interrupt Number.

R/W

VDD

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

VDD

03h

74h

Report no DMA assignment.

VDD

04h

75h

Report no DMA assignment.

VDD

04h

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