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PC87413 Fiches technique(PDF) 244 Page - National Semiconductor (TI) |
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PC87413 Fiches technique(HTML) 244 Page - National Semiconductor (TI) |
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244 / 257 page ![]() 11.0 Device Characteristics (Continued) www.national.com 244 Revision1.2 SERIRQ and LPC Signals Symbol Figure Description Reference Conditions Min Max Unit tVAL Output Output Valid Delay After RE CLK 11 ns tON Output Float to Active Delay After RE CLK 21 1. Not tested. Guaranteed by characterization. ns tOFF Output Active to Float Delay After RE CLK 281 ns tSU Input Input Setup Time Before RE CLK 7 ns tHL Input Input Hold Time After RE CLK 0 ns Leakage Only Leakage Only 0.285 VDD 0.615 VDD 0.4 VDD 0.4 VDD LCLK LAD3-LAD0, LDRQ, SERIRQ Outputs tVAL tON tOFF VDD = 3.3V ±10% tVAL LAD3-LAD0, SERIRQ Output Enabled 0.4 VDD 0.4 VDD LCLK LAD3-LAD0, LFRAME LRESET, SERIRQ Inputs VDD = 3.3V ±10% tHL tSU |
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