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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD6676EBZ Fiches technique(PDF) 85 Page - Analog Devices |
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AD6676EBZ Fiches technique(HTML) 85 Page - Analog Devices |
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85 / 90 page  Data Sheet AD6676 Rev. A | Page 85 of 90 Bits Bit Name Description Reset Access 5 MIX_NEXT Once set, only the next SYSREF pulse that is used to align the clock dividers is also used to reset the mixers NCO phases. This bit self clears after use. This bit is only active when Bit 1 is also active. 0x0 RWAC 4 MIX_ALL Any SYSREF that is used to align the clocks is also used to reset the mixers' NCO phases. This bit is only active when Bit 0 is also active. 0x0 RW 3 RESERVED 0x0 RW 2 USE_2ND_SYSREF When used in conjunction with Bit 1, setting this bit causes the second SYSREF to be used for alignment rather than the first. This bit does not self clear. 0x0 RW 1 NEXT_SYSREF Once set, only the next SYSREF pulse is used to align the clock dividers. This bit self- clears after the next SYSREF. 0x0 RWAC 0 ALL_SYSREF All SYSREF pulses are used to align the clock dividers. 0x0 RW LMFC Offset Register Address: 0x1E9, Reset: 0x00, Name: K_OFFSET Table 113. Bit Descriptions for K_OFFSET Bits Bit Name Description Reset Access [7:5] RESERVED 0x0 RW [4:0] K_OFFSET This register provides an offset that moves the position of the internal LMFC with respect to SYSREF. A larger value places the LMFC later in time. In units of frame periods. 0x00 RW SYSREF Window Register Address: 0x1EA, Reset: 0x00, Name: SYSREF Table 114. Bit Descriptions for SYSREF Bits Bit Name Description Reset Access [7:4] SYSREF_WIN_NEG SYSREF_WIN_NEG. Do not align clocks if SYSREF is no earlier than register value before its expected position. In units of 2/F ADC. 0x0 RW [3:0] SYSREF_WIN_POS SYSREF_WIN_POS. Do not align clocks if SYSREF is no later than register value after its expected position. In units of 2/F ADC. 0x0 RW PHY Control 0 Register Address: 0x1EB, Reset: 0x1C, Name: SER1 Table 115. Bit Descriptions for SER1 Bits Bit Name Description Reset Access 7 SER_DRV_PS Serializer Polarity Selection. 0x0 RW 0 = Polarity not inverted. 1 = Polarity inverted. [6:0] RESERVED 0x1C RW PHY Control 1 Register Address: 0x1EC, Reset: 0x00, Name: SER2 Table 116. Bit Descriptions for SER1 Bits Bit Name Description Reset Access [7:4] SER_ITRIM Driver bias current trim with recommended setting of 0x0B. 0x9 RW [3:0] SER_RTRIM Resistor termination code with recommended setting of 0x0D. 0xB RW |
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