AD6676EBZ datasheet(47/90 Pages) AD

47 / 90 page

Data Sheet

AD6676

Rev. A | Page 47 of 90

FUNCTIONAL OVERVIEW

The flowchart in Figure 120 shows the flow of data through the

JESD204B hardware from the sample input to the physical output.

The processing is divided into layers that are derived from the

OSI model widely used to describe the abstraction layers of

communications systems. These are the transport layer, the data

link layer, and the physical layer (serializer and output driver).

Transport Layer

The transport layer packs the data into JESD204B frames,

which are mapped to 8-bit octets that are sent to the data link

layer. The transport layer mapping is controlled by rules derived

from the link parameters. The AD6676 uses no tail bits in the

transport layer because the output of its IQ digital data path is

considered two virtual 16-bit converters.

Data Link Layer

The data link layer is responsible for the low level functions of

passing data across the link. These include optional data

scrambling, inserting control characters for lane alignment/

monitoring, and encoding 8-bit octets into 10-bit symbols. The

data link layer also sends the initial lane alignment sequence

(ILAS), which contains the link configuration data, and is used

by the receiver to verify the settings in the transport layer.

Physical Layer

The physical layer consists of the high speed circuitry clocked at

the serial clock rate. For the AD6676, the 16-bit I and Q data are

converted into one or two lanes of high speed differential serial data.

JESD204B LINK ESTABLISHMENT

The AD6676 JESD204B Tx interface operates in Subclass 0 or

Subclass 1 as defined in the JEDEC Standard No. 204B (July 2011)

specification. The link establishment process is divided into the

following steps: code group synchronization, ILAS, and user data.

Code Group Synchronization (CGS) and SYNCINB

Code group synchronization (CGS) is the process where the

JESD204B receiver finds the boundaries between the 10-bit

symbols in the stream of data. During the CGS phase, the

JESD204B transmit (JESD Tx) block transmits /K28.5/ characters.

The receiver must locate /K28.5/ characters in its input data

stream using clock and data recovery (CDR) techniques.

The receiver issues a synchronization request by asserting a low

signal on the SYNCINB± pins of the AD6676. The JESD Tx

begins to send /K/ characters. After the receiver has synchronized,

it then deasserts its SYNCINB signal, causing it to go high. The

AD6676 then transmits an ILAS on the following LMFC boundary.

For more information on the CGS phase, see the JEDEC

Standard No. 204B (July 2011), Section 5.3.3.1.

The SYNCINB± pin operation options are controllable via SPI

registers. Although the SYNCINB input is configured for a

CMOS logic level on its positive pin by default, it can also be

configured for a differential LVDS input signal on its positive/

negative pins via Register 0x1E7. The polarity of the SYNCINB

input signal can also be inverted via Register 0x1E4.

Initial Lane Alignment Sequence (ILAS)

The ILAS phase follows the CGS phase and begins on the next

LMFC boundary. The ILAS consists of four multiframes, with a

/R/ character marking the beginning and an /A/ character

marking the end. The ILAS begins by sending an /R/ character

followed by a data ramp starting with the value, 0, over four

multiframes. On the second multiframe, the link configuration

data is sent, starting with the third character. The second character

in the second multiframe is a /Q/ character to confirm that the

link configuration data follows. All undefined data slots are

filled with ramp data. The ILAS sequence is never scrambled.

The ILAS sequence construction is shown in Figure 121. The

four multiframes include the following:

•

Multiframe 1: Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

•

Multiframe 2: Begins with an /R/ character followed by a

/Q/ (/K28.4/) character, followed by link configuration

parameters over 14 configuration octets (see Table 18), and

ends with an /A/ character. Many of the parameter values

are of the notation of n − 1.

•

Multiframe 3: Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

•

Multiframe 4: Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

User Data and Error Detection

After the ILAS is complete, the user data is sent. Normally, in a

frame all characters are user data. However, to monitor the

frame clock and multiframe clock synchronization, there is a

mechanism for replacing characters with /F/ or /A/ alignment

characters when the data meets certain conditions. These

conditions are different for unscrambled and scrambled data.

The scrambling operation is disabled by default, but may be

enabled via Register 0x1C3.

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