AD6676EBZ datasheet(42/90 Pages) AD

42 / 90 page

AD6676

Data Sheet

Rev. A | Page 42 of 90

0.5

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

FREQUENCY NORMALIZED TO

fDATA_IQ

Figure 111. Pass Band Frequency Response of Decimate by 32

–120

–100

–80

–60

–40

–20

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

FREQUENCY NORMALIZED TO

fDATA_IQ

MINIMUM ALIAS ATTENUATION 88dB

Figure 112. Folded Frequency Response of Decimate by 32 Shows Alias

Rejection

AGC FEATURES AND PEAK DETECTION

In receiver applications, it is desirable to have a mechanism to

reliably determine when the converter is about to be overdriven.

The AD6676 Σ-Δ ADC is based on a feedback loop that can be

overdriven into a nonlinear region, resulting in oscillation. This

oscillation persists until the Σ-Δ ADC is reset and the overload

condition is removed. Typically, a receiver lineup employs some

form of AGC that attempts to avoid this scenario.

The AD6676 pipeline latency along with any additional

overhead associated with the host processor (JESD204B Rx

PHY) may limit the ability to design a fast reacting digital-based

AGC required by some applications. For this reason, the

AD6676 includes the AGCx pins that serve as digital input/

outputs to facilitate the implementation of a fast AGC control

loop under the control of the host. The AGC4 and AGC3 pins

can be allocated to provide flag outputs after a programmable

threshold has been exceeded, including an ADC reset event,

while the AGC2 and AGC1 pins can be used to control the on-

chip attenuator. Register 0x18F and Register 0x193 through

Peak Detection and AGC Flags

Peak detection occurs at the output of the second stage decimation

filter, as shown in Figure 103. Detection at this stage represents a

compromise between the accuracy of the peak detector, delay time

and ability to measure large out-of-band signals. At this stage, the

Σ-Δ ADC output signal has been frequency translated to dc and its

out-of-band noise sufficiently filtered for reasonable threshold

detection accuracy down to −12 dBFS peak signal levels. Note that

the peak detector monitors the peak power envelope response of

the IF input signal and calculates the peak power (that is, I2 + Q2)

expressed in dBFS with 12-bit resolution.

Because the peak detector is monitoring the peak power at the

output of the second stage decimation filter, it provides a wider

frequency range than what can be observed in the final IQ data

output. The first stage filter is decimate by 3 or by 4; therefore,

the output of the second stage filter can be 1/6th or 1/8th of FADC.

Figure 113 shows the normalized measurement bandwidth relative

to the output rate of the second stage filter centered about its zero

IF. Table 16 references the measurement bandwidth to fDATA_IQ for

the different decimation factors such that its absolute bandwidth

can be easily determined. For example, the −1 dB bandwidth for an

fDATA_IQ of 100 MSPS with decimate by 24 or by 32 is 200 MHz and

remains at 200 MHz if the decimation factor is reduced to decimate

by 12 or by 16. Any droop occurring at the pass band edges, as well

as the Σ-Δ ADC STF, must be considered when setting thresholds.

0.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

FREQUENCY OFFSET FROM IF CENTER

(NORMALIZED TO FIQ@2ND STAGE FILTER)

–0.35

–0.25

–0.15

–0.05

0.05

0.15

0.25

0.35

Figure 113. Normalized Pass Band Filter Response Seen by the Peak Detector

Table 16. Normalized Measurement Bandwidth of Peak

Detector Relative to Output Data Rate, fDATA_IQ

DEC_

MODE

Decimation

Factor

Normalized Measurement Bandwidth

Relative to

DATA_IQ

−0.5

dBFS

−1.0

dBFS

−2.0

dBFS

−3.0

dBFS

1.76

2.00

2.40

2.64

1.76

2.00

2.40

2.64

0.88

1.00

1.20

1.32

0.88

1.00

1.20

1.32

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