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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD6676EBZ Fiches technique(PDF) 84 Page - Analog Devices |
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AD6676EBZ Fiches technique(HTML) 84 Page - Analog Devices |
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84 / 90 page  AD6676 Data Sheet Rev. A | Page 84 of 90 Interface Test Register Address: 0x1E5, Reset: 0x00, Name: TEST_GEN Table 109. Bit Descriptions for TEST_GEN Bits Bit Name Settings Description Reset Access [7:6] RESERVED 0x0 RW [5:4] TEST_GEN_SEL Test Point. 0x0 RW 00 Insert test data at framer input (16 bits). 01 Insert test data at PHY input (10 bits). 10 Insert test data at scrambler input (8 bits). [3:0] TEST_GEN_MODE Test Mode. 0x0 RW 0000 Normal mode; test disabled. 0001 Alternating checkerboard. 0010 1/0 word toggle. 0011 Long PN sequence. 0100 Short PN sequence. 0101 Repeating user pattern mode. 0110 Single user pattern mode. 0111 Ramp. Note that in single lane mode the Q sample is 1 LSB less than the I sample. In other words, Q[n] = I[n] – 1 LSB, where n is nth IQ sample. 1000 Modified RPAT sequence. 1001 Not used. 1010 JSPAT sequence. 1011 JTSPAT sequence. ILAS Count Register Address: 0x1E6, Reset: 0x00, Name: KF_ILAS Table 110. Bit Descriptions for KF_ILAS Bits Bit Name Description Reset Access [7:0] KF_ILAS Initial Lane Assignment Sequence Count. The ILAS is transmitted (KF_ILAS + 1) times. 0x00 RW SYNCINB and SYSREF Control Register Address: 0x1E7, Reset: 0x00, Name: SYNCINB_CTRL Table 111. Bit Descriptions for SYNCB_CTRL Bits Bit Name Description Reset Access [7:4] RESERVED 0x0 RW 3 PD_SYSREF_RX Power down SYSREF receiver. 0x0 RW 2 LVDS_SYNCINB Use LVDS for SYNCINB. (0 = CMOS, 1 = LVDS differential with 100 Ω termination). 0x0 RW [1:0] RESERVED 0x0 RW Clock Synchronization Register Address: 0x1E8, Reset: 0x00, Name: MIX_CTRL Table 112. Bit Descriptions for MIX_CTRL Bits Bit Name Description Reset Access 7 RESERVED 0x0 RW 6 MIX_USE_2ND When used in conjunction with Bit 5, setting this bit causes the second SYSREF that is used to align the clocks to also be used to reset the mixer NCO phases. This bit does not self-clear. This bit is only active when Bit 2 is also active. 0x0 RW |
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