AD6676EBZ datasheet(82/90 Pages) AD

82 / 90 page

AD6676

Data Sheet

Rev. A | Page 82 of 90

JESD204 FCHK0 Register

Address: 0x1D8, Reset: 0x44, Name: FCHK0

Table 102. Bit Descriptions for FCHK0

Bits

Bit Name

Description

Reset

Access

[7:0]

FCHK0

Checksum for Lane 0.

0x44

JESD204 FCHK1 Register

Address: 0x1D9, Reset: 0x45, Name: FCHK1

Table 103. Bit Descriptions for FCHK1

Bits

Bit Name

Description

Reset

Access

[7:0]

FCHK1

Checksum for Lane 1.

0x45

Enable Lane FIFO Register

Address: 0x1E0, Reset: 0x00, Name: EN_LFIFO

Table 104. Bit Descriptions for EN_LFIFO

Bits

Bit Name

Description

Reset

Access

[7:1]

RESERVED

0x00

EN_LFIFO

Lane FIFO Enable. Once the entire configuration of the framer has been completed, and the

link is powered up, set this bit to start the lane FIFOs that manage the hand-off of data from

the framer to the transmitter PHY.

0x0

Swap Register

Address: 0x1E1, Reset: 0x00, Name: SWAP

Table 105. Bit Descriptions for SWAP

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

RESERVED

0x0

[5:4]

SWAP_CONV

Bit [4] swaps the source of Framer Converter 0 (default is I channel).

0x0

Bit [5] swaps the source of Framer Converter 1 (default is Q channel).

Framer Input 1 = Q channel; Framer Input 0 = I channel

Framer Input 1 = Q channel; Framer Input 0 = Q channel

Framer Input 1 = I channel; Framer Input 0 = I channel

Framer Input 1 = I channel; Framer Input 0 = Q channel

[3:2]

RESERVED

0x0

[1:0]

SWAP_LANE

Bit [0] swaps the source of physical output lane 0.

0x0

Bit [1] swaps the source of physical output lane 1.

Output Lane 1 = Famer lane 1; Output Lane 0 = Framer Lane 0

Output Lane 1 = Framer lane 1; Output Lane 0 = Framer Lane 1

Output Lane 1 = Framer lane 0; Output Lane 0 = Framer Lane 0

Output Lane 1 = Framer lane 0; Output Lane 0 = Framer Lane 1

AD6676EBZ Fiches technique(PDF) 82 Page - Analog Devices

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