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AD6676EBZ Fiches technique(PDF) 83 Page - Analog Devices

No de pièce AD6676EBZ
Description  Wideband IF Receiver Subsystem
PDF  90 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD6676EBZ Fiches technique(HTML) 83 Page - Analog Devices

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Data Sheet
AD6676
Rev. A | Page 83 of 90
Link/Lane Power-Down Register
Address: 0x1E2, Reset: 0x00, Name: LANE_PD
Table 106. Bit Descriptions for LANE_PD
Bits
Bit Name
Description
Reset
Access
[7:4]
ILAS_DELAY
ILAS Start Delay. Usually the ILAS starts on the first LMFC rising edge after
SYNCINB goes high. This value delays the ILAS by the given number of LMFC
periods (multiframe periods).
0x0
RW
[3:2]
RESERVED
0x0
RW
[1:0]
LANE_PD
Lane Power-down.
0x0
RW
Bit 0 powers down transmitter PHY for Lane 0.
Bit 1 powers down transmitter PHY for Lane 1.
Interface Control 0 Register
Address: 0x1E3, Reset: 0x14, Name: MIS1
Table 107. Bit Descriptions for MIS1
Bits
Bit Name
Description
Reset
Access
[7:6]
RESERVED
0x0
RW
5
TEST_SAMPLE_EN
0 = Disable transport layer test samples.
0x0
RW
1 = Enable transport layer test samples.
4
LSYNC_EN
0 = Disable lane synchronization.
0x1
RW
1 = Enable lane synchronization (default).
[3:2]
ILAS_MODE
01 = Enable ILAS (default).
0x1
RW
11 = ILAS always on; data link layer test mode.
1
FACI_DISABLE
Control of Frame Alignment Characters.
0x0
RW
0 = Enable frame alignment character insertion.
1 = Disable frame alignment character insertion.
0
RESERVED
0x0
RW
Interface Control 1 Register
Address: 0x1E4, Reset: 0x00, Name: SYNC_PIN
Table 108. Bit Descriptions for SYNC_PIN
Bits
Bit Name
Description
Reset
Access
[7:6]
RESERVED
0x0
RW
5
SYNC_PIN_INV
0 = do not invert SYNCINB pin; SYNCINB is active low.
0x0
RW
1 = invert SYNCINB pin; SYNCINB is active high.
[4:2]
RESERVED
0x0
RW
1
INV_10B
0 = do not invert octets.
0x0
RW
1 = invert all bits in 10-bit octets from framer. Setting the bit to 1 has the same effect
as swapping the differential output data pins.
0
RESERVED
0x0
RW



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