AD6676EBZ datasheet(43/90 Pages) AD

43 / 90 page

Data Sheet

AD6676

Rev. A | Page 43 of 90

The AD6676 allows the user to set three threshold settings that

can trigger one of two possible flags. PKTHRH0 and PKTHRH1

are two upper threshold settings while LOWTHRH is a lower

threshold setting. The threshold settings are 12 bits with an

MSB and LSB register assigned to each threshold. The 12-bit

decimal equivalent value can be calculated using Equation 12.

Threshold = 3584 + (Threshold Setting in dBFS) × 256/3 (12)

where 0 dBFS corresponds to 3584 (0xE00) and −6 dBFS

corresponds to 3072 (0xC00).

In the time domain, a 0 dBFS setting corresponds to a signal

whose peaks observed at the I and Q outputs can reach plus or

minus full scale. Meaning, if the 16-bit I and Q output data are

normalized such that its peak values correspond to ±1, a 0 dBFS

setting corresponds to a signal whose peak can reach the unit

circle of a normalized I/Q constellation diagram.

The LOWTHRH_x register has an associated dwell time of

which the signal must remain below this threshold before a flag

can be set. The dwell time is represented in exponential form to

realize long dwell periods because the counter operates at

FADC/12 for decimate by 12 or 24 settings or FADC/16 for decimate

by 16 or 32 settings. The dwell time is set in the DWELL_TIME_

MANTISSA register and DWELL_TIME_EXP register using

Equation 13 relative to 1/FADC.

Dwell Time = N × [DWELL_TIME_MANTISSA] ×

2(DWELL_TIME_EXP)

(13)

where:

N = 12 for decimate by 12 or 24.

N = 16 for decimate by 16 or 32.

A flag function can be assigned using the FLAG0_SEL register

and FLAG1_SEL register to indicate when any of the thresholds

have been exceeded or if an ADC reset event has occurred.

These flags must also be enabled via the EN_FLAG register

such that a CMOS level signal appears on the AGC4 and AGC3

pins where a logic high indicates when a threshold has been

exceeded.

The delay relative to the ADC input when an AGC threshold is

exceeded to when the flag signal goes high is dependent on the

DEC_MODE setting selected. For a DEC_MODE value of 1 or

2 (decimate by 32 or 24), the delay equates to 8 to 9 output

samples (1/fDATA_IQ). For DEC_MODE values of 3 or 4 (decimate

by 16 or 12), the delay is 16 to 18 samples. The delay associated

with an ADC reset event is much shorter because it avoids the

digital filter path. This delay is 1 sample for DEC_MODE values

of 1 or 2 and 2 samples for DEC_MODE values of 3 and 4.

Note that the EN_FLAGx bits provide the additional option of

logically OR’ing an ADC reset event with an upper peak

threshold event to provide an even faster output flag to the host

processor indicating that the attenuation must be applied. This

scenario applies to the extreme case where the envelope

response of a blocker is exceedingly fast, such that the AGC

cannot react fast enough to the upper peak threshold setting

flag to prevent overloading the Σ-Δ ADC.

Figure 114 provides an example of how the Flag 0 and Flag 1

assigned pins behave to the envelope response of an arbitrary IF

input signal. Flag 1 is assigned an upper threshold set by

PKTHRH1_x, and Flag 0 is assigned a lower threshold and

dwell time set by LOWTHRH_x and DWELL_TIME_x. The

Flag 1 indicator goes high when the PKTTHR1_x threshold is

exceeded and returns low when the signal envelope falls below

this threshold. The Flag 0 indicator goes high only when the

envelope of the signal remains below the LOWTHRH_x

threshold for the designated dwell time. If the signal level

exceeds the LOWTHRH_x threshold before the dwell time

counter has expired, the dwell time counter resets again and the

Flag 0 indicator remains low until the conditions has been met.

By offsetting the PKTTHR1_x and LOWTHRH_x threshold

settings as well as optimizing the dwell time setting, it may be

possible to optimize the operation of an AGC so that it reacts to

signal strength variation due to fading conditions as opposed to the

peak to minimum response associated with digital modulated

signals.

IF Attenuator Control via the AGC2 and AGC1 Pins

Many AGC implementations require fast gain control if the

AGC threshold is exceeded. The AD6676 provides two modes in

which the IF attenuator can be quickly changed via the AGCx pins.

Use Register 0x180, Bit 0, to select the mode. The first mode uses

the AGC2 pin to switch between two attenuator settings that are

user defined in Register 0x181 and Register 0x182. The second

mode uses the AGC2 and AGC1 pins to decrement and increment

respectively the attenuation value in 1 dB steps with pulsed inputs.

The starting attenuator value is defined in Register 0x183. The

actual attenuator value can be read back via Register 0x184.

The first mode is used for the default AD6676 power-up setting

with both Register 0x181 and Register 0x182 set to 0x0C. For

applications that do not require IF attenuator control but

require a different attenuator setting, update both registers with

the desired attenuator setting value such that the attenuator

remains independent of the AGC2 pin state, if it is left floating.

Note that connecting the unused AGC2 and AGC1 pins to

VSSD via 100 kΩ pull-down resistors is still the preferred

method if these pins are unused.

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