CY8C56LP datasheet(26/120 Pages) CYPRESS

26 / 120 page

PRELIMINARY

PSoC® 5LP: CY8C56LP Family

Datasheet

Document Number: 001-84935 Rev. **

Page 26 of 120

Figure 6-5. Power Mode Transitions

6.2.1.1

Active Mode

Active mode is the primary operating mode of the device. When

in active mode, the active configuration template bits control

which available resources are enabled or disabled. When a

resource is disabled, the digital clocks are gated, analog bias

currents are disabled, and leakage currents are reduced as

appropriate. User firmware can dynamically control subsystem

power by setting and clearing bits in the active configuration

template. The CPU can disable itself, in which case the CPU is

automatically reenabled at the next wakeup event.

When a wakeup event occurs, the global mode is always

returned to active, and the CPU is automatically enabled,

regardless of its template settings. Active mode is the default

global power mode upon boot.

6.2.1.2

Alternate Active Mode

Alternate Active mode is very similar to Active mode. In alternate

active mode, fewer subsystems are enabled, to reduce power

consumption. One possible configuration is to turn off the CPU

and flash, and run peripherals at full speed.

6.2.1.3

Sleep Mode

Sleep mode reduces power consumption when a resume time of

15 µs is acceptable. The wake time is used to ensure that the

regulator outputs are stable enough to directly enter active

mode.

6.2.1.4

Hibernate Mode

In hibernate mode nearly all of the internal functions are

disabled. Internal voltages are reduced to the minimal level to

keep vital systems alive. Configuration state is preserved in

hibernate mode and SRAM memory is retained. GPIOs

configured as digital outputs maintain their previous values and

external GPIO pin interrupt settings are preserved. The device

can only return from hibernate mode in response to an external

I/O interrupt. The resume time from hibernate mode is less than

100 µs.

To achieve an extremely low current, the hibernate regulator has

limited capacity. This limits the frequency of any signal present

on the input pins; no GPIO should toggle at a rate greater than

10 kHz while in hibernate mode. If pins must be toggled at a high

rate while in a low power mode, use sleep mode instead.

6.2.1.5

Wakeup Events

Wakeup events are configurable and can come from an interrupt

or device reset. A wakeup event restores the system to active

mode. Firmware enabled interrupt sources include internally

generated interrupts, power supervisor, central timewheel, and

I/O interrupts. Internal interrupt sources can come from a variety

of peripherals, such as analog comparators and UDBs. The

central timewheel provides periodic interrupts to allow the

system to wake up, poll peripherals, or perform real-time

functions. Reset event sources include the external reset I/O pin

(XRES), WDT, and Precision Reset (PRES).

6.2.2 Boost Converter

Applications that use a supply voltage of less than 1.71 V, such

as single cell battery supplies, may use the on-chip boost

converter. The boost converter may also be used in any system

that requires a higher operating voltage than the supply provides.

For instance, this includes driving 5.0 V LCD glass in a 3.3 V

system. The boost converter accepts an input voltage as low as

0.5 V. With one low cost inductor it produces a selectable output

voltage sourcing enough current to operate the PSoC and other

on-board components.

The boost converter accepts an input voltage VBAT from 0.5 V

to 3.6 V, and can start up with VBAT as low as 0.5 V. The

converter provides a user configurable output voltage of 1.8 to

5.0 V (VBOOST). VBAT is typically less than VBOOST; if VBAT

is greater than or equal to VBOOST, then VBOOST will be the

same as VBAT. The block can deliver up to 75 mA (IBOOST)

depending on configuration.

Four pins are associated with the boost converter: VBAT, VSSB,

VBOOST, and Ind. The boosted output voltage is sensed at the

VBOOST pin and must be connected directly to the chip’s supply

inputs. An inductor is connected between the VBAT and Ind pins.

You can optimize the inductor value to increase the boost

converter efficiency based on input voltage, output voltage,

current and switching frequency.

Figure 6-6. Application for Boost Converter

Active

Manual

Hibernate

Alternate

Active

Sleep

PSoC

VBOOST

IND

VBAT

VSSB

VSSD

VDDA

VDDD

VSSA

22 µF 0.1 µF

22 µF

10 µH

Schottky diode

CY8C56LP Fiches technique(PDF) 26 Page - Cypress Semiconductor

CY8C56LP Fiches technique(HTML) 26 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL