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CY8C56LP Fiches technique(PDF) 84 Page - Cypress Semiconductor

No de pièce CY8C56LP
Description  Programmable System-on-Chip (PSoC짰)
PDF  120 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C56LP Fiches technique(HTML) 84 Page - Cypress Semiconductor

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PRELIMINARY
PSoC® 5LP: CY8C56LP Family
Datasheet
Document Number: 001-84935 Rev. **
Page 84 of 120
Figure 11-33. SAR ADC Noise Histogram, 1000 samples,
700 ksps, Internal Reference No Bypass, VIN = VREF/2
Figure 11-34. SAR ADC Noise Histogram, 1000
samples, 700 ksps, Internal Reference Bypassed, VIN =
VREF/2
Figure 11-35. SAR ADC Noise Histogram, 1000 samples,
700 ksps, External Reference, VIN = VREF/2
Table 11-25. SAR ADC AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Fclk
SAR clock frequency
1
–
18
MHz
Tc
Conversion time
One conversion requires 18 SAR
clocks. Maximum sample rate is 1
Msps
1
–
18
µs
Startup time[44]
–
–
10
µs
SINAD
Signal-to-noise ratio[44]
68
–
–
dB
THD
Total harmonic distortion[44]
–
–
0.02
%
Note
44. Based on device characterization (Not production tested).



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