CY8C56LP datasheet(39/120 Pages) CYPRESS

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PSoC® 5LP: CY8C56LP Family

Datasheet

Document Number: 001-84935 Rev. **

Page 39 of 120

7.2.2.8

Conditionals

Each datapath has two compares, with bit masking options.

Compare operands include the two accumulators and the two

data registers in a variety of configurations. Other conditions

include zero detect, all ones detect, and overflow. These

conditions are the primary datapath outputs, a selection of which

can be driven out to the UDB routing matrix. Conditional

computation can use the built in chaining to neighboring UDBs

to operate on wider data widths without the need to use routing

resources.

7.2.2.9

Variable MSB

The most significant bit of an arithmetic and shift function can be

programmatically specified. This supports variable width CRC

and PRS functions, and in conjunction with ALU output masking,

can implement arbitrary width timers, counters and shift blocks.

7.2.2.10 Built in CRC/PRS

The datapath has built in support for single cycle Cyclic

Redundancy Check (CRC) computation and Pseudo Random

Sequence (PRS) generation of arbitrary width and arbitrary

polynomial. CRC/PRS functions longer than 8 bits may be

implemented in conjunction with PLD logic, or built in chaining

may be use to extend the function into neighboring UDBs.

7.2.2.11 Input/Output FIFOs

Each datapath contains two four-byte deep FIFOs, which can be

independently configured as an input buffer (system bus writes

to the FIFO, datapath internal reads the FIFO), or an output

buffer (datapath internal writes to the FIFO, the system bus reads

from the FIFO). The FIFOs generate status that are selectable

as datapath outputs and can therefore be driven to the routing,

to interact with sequencers, interrupts, or DMA.

Figure 7-5. Example FIFO Configurations

7.2.2.12 Chaining

The datapath can be configured to chain conditions and signals

such as carries and shift data with neighboring datapaths to

create higher precision arithmetic, shift, CRC/PRS functions.

7.2.2.13 Time Multiplexing

In applications that are over sampled, or do not need high clock

rates, the single ALU block in the datapath can be efficiently

shared with two sets of registers and condition generators. Carry

and shift out data from the ALU are registered and can be

selected as inputs in subsequent cycles. This provides support

for 16-bit functions in one (8-bit) datapath.

7.2.2.14 Datapath I/O

There are six inputs and six outputs that connect the datapath to

the routing matrix. Inputs from the routing provide the

configuration for the datapath operation to perform in each cycle,

and the serial data inputs. Inputs can be routed from other UDB

blocks, other device peripherals, device I/O pins, and so on. The

outputs to the routing can be selected from the generated

conditions, and the serial data outputs. Outputs can be routed to

other UDB blocks, device peripherals, interrupt and DMA

controller, I/O pins, and so on.

7.2.3 Status and Control Module

The primary purpose of this circuitry is to coordinate CPU

firmware interaction with internal UDB operation.

Figure 7-6. Status and Control Registers

System Bus

A0/A1/ALU

D0/D1

A0/A1/ALU

System Bus

A0/A1/ALU

System Bus

TX/RX

Dual Capture

Dual Buffer

Routing Channel

8-bit Status Register

(Read Only)

8-bit Control Register

(Write/Read)

System Bus

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