CY8C56LP datasheet(50/120 Pages) CYPRESS

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PSoC® 5LP: CY8C56LP Family

Datasheet

Document Number: 001-84935 Rev. **

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8.2 Delta-sigma ADC

Some CY8C36 devices offer a delta-sigma ADC. This ADC

offers differential input, high resolution and excellent linearity,

making it a good ADC choice for measurement applications. The

converter can be configured to output 12-bit resolution at data

rates of up to 192 ksps. At a fixed clock rate, resolution can be

traded for faster data rates as shown in Table 8-1 and Figure 8-3.

Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024 V

8.2.1 Functional Description

The ADC connects and configures three basic components,

input buffer, delta-sigma modulator, and decimator. The basic

block diagram is shown in Figure 8-4. The signal from the input

muxes is delivered to the delta-sigma modulator either directly or

through the input buffer. The delta-sigma modulator performs the

actual analog to digital conversion. The modulator over-samples

the input and generates a serial data stream output. This high

speed data stream is not useful for most applications without

some type of post processing, and so is passed to the decimator

through the Analog Interface block. The decimator converts the

high speed serial data stream into parallel ADC results. The

modulator/decimator frequency response is [(sin x)/x]4.

Figure 8-4. Delta-sigma ADC Block Diagram

Resolution and sample rate are controlled by the Decimator.

Data is pipelined in the decimator; the output is a function of the

last four samples. When the input multiplexer is switched, the

output data is not valid until after the fourth sample after the

switch.

8.2.2 Operational Modes

The ADC can be configured by the user to operate in one of four

modes: Single Sample, Multi Sample, Continuous, or Multi

Sample (Turbo). All four modes are started by either a write to

the start bit in a control register or an assertion of the Start of

Conversion (SoC) signal. When the conversion is complete, a

status bit is set and the output signal End of Conversion (EoC)

asserts high and remains high until the value is read by either the

DMA controller or the CPU.

8.2.2.1

Single Sample

In Single Sample mode, the ADC performs one sample

conversion on a trigger. In this mode, the ADC stays in standby

state waiting for the SoC signal to be asserted. When SoC is

signaled the ADC performs four successive conversions. The

first three conversions prime the decimator. The ADC result is

valid and available after the fourth conversion, at which time the

EoC signal is generated. To detect the end of conversion, the

system may poll a control register for status or configure the

external EoC signal to generate an interrupt or invoke a DMA

request. When the transfer is done the ADC reenters the standby

state where it stays until another SoC event.

8.2.2.2

Continuous

Continuous sample mode is used to take multiple successive

samples of a single input signal. Multiplexing multiple inputs

should not be done with this mode. There is a latency of three

conversion times before the first conversion result is available.

This is the time required to prime the decimator. After the first

result, successive conversions are available at the selected

sample rate.

8.2.2.3

Multi Sample

Multi sample mode is similar to continuous mode except that the

ADC is reset between samples. This mode is useful when the

input is switched between multiple signals. The decimator is

re-primed between each sample so that previous samples do not

affect the current conversion. Upon completion of a sample, the

next sample is automatically initiated. The results can be

transferred using either firmware polling, interrupt, or DMA.

More information on output formats is provided in the Technical

Reference Manual.

Table 8-1. Delta-sigma ADC Performance

Bits

Maximum Sample Rate

(sps)

SINAD (dB)

192 k

384 k

100

1,000

10,000

100,000

1,000,000

10111213

Continuous

Multi-Sample

Resolution, bits

Delta

Sigma

Modulator

Decimator

12 to 20 Bit

Result

EOC

SOC

Positive

Input Mux

Negative

Input Mux

(Analog Routing)

Input

Buffer

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