CY8C56LP datasheet(6/120 Pages) CYPRESS

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PRELIMINARY

PSoC® 5LP: CY8C56LP Family

Datasheet

Document Number: 001-84935 Rev. **

Page 6 of 120

Figure 2-3. 68-pin QFN Part Pinout[5]

(TRACEDATA[2], GPIO) P2[6]

(TRACEDATA[3], GPIO) P2[7]

(I2C0: SCL, SIO) P12[4]

(I2C0: SDA, SIO) P12[5]

VSSB

IND

VBOOST

VBAT

VSSD

XRES

(TMS, SWDIO, GPIO) P1[0]

(TCK, SWDCK, GPIO) P1[1]

(Configurable XRES, GPIO) P1[2]

(TDO, SWV, GPIO) P1[3]

(TDI, GPIO) P1[4]

(NTRST, GPIO) P1[5]

VDDIO1

P0[3] (GPIO, OPAMP0-/EXTREF0)

P0[2] (GPIO, OPAMP0+/SAR1 EXTREF)

P0[1] (GPIO, OPAMP0OUT)

P0[0] (GPIO, OPAMP2OUT)

P12[3] (SIO)

P12[2] (SIO)

VSSD

VDDA

VSSA

VCCA

P15[3] (GPIO, KHZ XTAL: XI)

P15[2] (GPIO, KHZ XTAL: XO)

P12[1] (SIO, I2C1: SDA)

P12[0] (SIO, 12C1: SCL)

P3[7] (GPIO, OPAMP3OUT)

P3[6] (GPIO, OPAMP1OUT)

VDDIO3

QFN

(TOP VIEW)

Lines show VDDIO

to I/O supply

association

Notes

5. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

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