SPEAR300 datasheet(25/83 Pages) STMICROELECTRONICS

25 / 83 page

SPEAr300

Architecture overview

Doc ID 16324 Rev 2

25/83

2.24

Ethernet controller

SPEAr300 provides an Ethernet MAC 10/100 Universal (commonly referred to as GMAC-

UNIV), enabling to transmit and receive data over Ethernet in compliance with the IEEE

802.3-2002 standard.

Note:

GMAC is a hardware block implementing Ethernet MAC layer 2 processing. GMAC is

configured for 10/100 Mbps operation on SPEAr3xx family and up to 1 Gbps on SPEAr600.

Main features:

●

Compliant with the IEEE 802.3-2002 standard

●

Supports the default MII interface to the external PHY

●

Supports 10/100 Mbps data transfer rates

●

Local FIFO available (4 Kbyte RX, 2 Kbyte TX)

●

Supports both half-duplex and full-duplex operation. In half-duplex operation,

CSMA/CD protocol is provided for, as well as packet bursting and frame extension at

100 Mbps

●

Programmable frame length to support both standard and jumbo Ethernet frames with

size up to 16 Kbyte

●

A variety of flexible addresses filtering modes are supported

●

A set of control and status registers (CSRs) to control MAC core operation

●

Native DMA with single-channel transmit and receive engines

●

DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining

●

An AHB slave acting as programming interface to access all CSRs, for both DMA and

MAC core subsystems

●

An AHB master for data transfer to system memory

●

32-bit AHB master bus width, supporting 32, 64, and 128-bit wide data transactions

●

It supports both little and big endian memory architectures

2.25

USB2 host controller

SPEAr300 has a fully independent USB 2.0 host controller, consisting of the following six

major blocks:

●

An EHCI block for high-speed transfers (HS mode, 480 Mbps)

●

2 OHCI blocks for full and low speed transfers (FS and LS modes, 12 and 1.5 Mbps)

●

Local 2-Kbyte FIFO

●

Local DMA

●

Integrated USB2 transceiver (PHY)

This host can manage an external power switch, providing a control line to enable or disable

the power, and an input line to sense any over-current condition detected by the external

switch.

The Host controller is capable of managing two different devices at a time on its two

downstream ports.

●

An HS device connected to either of the two ports is managed by the EHCI.

●

An FS/LS device connected to port0 is managed by OHCI0.

●

An FS/LS device connected to port1 is managed by OHCI1.

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