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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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SPEAR300 Fiches technique(PDF) 11 Page - STMicroelectronics |
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SPEAR300 Fiches technique(HTML) 11 Page - STMicroelectronics |
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11 / 83 page  SPEAr300 Architecture overview Doc ID 16324 Rev 2 11/83 2 Architecture overview The SPEAr300 internal architecture is based on several shared subsystem logic blocks interconnected through a multilayer interconnection matrix. The switch matrix structure allows different subsystem dataflow to be executed in parallel improving the core platform efficiency. High performance master agents are directly interconnected with the memory controller reducing the memory access latency. The overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted round- robin arbitration mechanism. Figure 2. SPEAr300 overview 2.1 ARM926EJ-S CPU The core of the SPEAr300 is an ARM926EJ-S reduced instruction set computer (RISC) processor. It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of Java byte codes. The ARM CPU and is clocked at a frequency up to 333 MHz. It has a 16-Kbyte instruction cache, a 16-Kbyte data cache, and features a memory management unit (MMU) which makes it fully compliant with Linux and WindowsCE operating systems. It also includes an embedded trace module (ETM Medium+) for real-time CPU activity tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode, with normal or half-rate clock. TouchScreen Keypad controller Internet access SPEAr300 ADC GPIO FSMC NOR Flash NOR Flash NAND Flash NAND Flash SRAM SRAM LCD controller USB2.0 PHY USB2.0 PHY Phy SPEAr300 ARM 926EJ up to 333 MHz 57 KB embed. SRAM 32 KB embed. ROM MMU DDR memory controller DDR2 DDR2 Mobile DDR Mobile DDR EEPROM EEPROM SMI Flash Flash USB2.0 PHY USB2.0 PHY USB2.0 PHY USB2.0 PHY 8-channel DMA 3 Timers / WD Standard OS support Interrupt/syst controller SDIO/MMC MMC MMC SD-Card SD-Card SDIO SDIO controller Mobile DDR Mobile DDR Db t Db t JTAG I2C JPEG Codec accelerator C3 Crypto accelerator IdDA Clock, reset 32 kHz 24 MHz RTC Camera interface Debug, trace Debug, trace ETM9 I2C I2S Audio CODECs TDM External CODEC/SLICs Note: Some interfaces share I/Os. Not all interfaces shown in the figure can be used Note: Some interfaces share I/Os. Not all interfaces shown in the figure can be used concurrently |
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