STLC5464 datasheet(61/83 Pages) STMICROELECTRONICS

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: Transparent Connection

TC = 1, if READ = 0 :

CAC = 0 and CACL = 0. The DSTR bits are taken into account instead of SRCR bits. SRCR bits

are ignored (Destination and Source are identical). The contents of Input time slot i - Input

multiplex j is switched into Output time slot i - Output multiplex j.

CAC = 0 and CACL = 1. Up to 32 ”Transparent Connections” are set up.

CAC = 1 and CACL = 0. Up to 256 ”Transparent Connections” are set up.

TC = 0, Write and Read Connection Memory in the normal way.

VIII.10 - Sequence Fault Counter Register - SFCR (12)H

bit15

bit8

bit7

bit 0

F15

F14

F13

F12

F11

F10

F8F7F6

F5F4

F3F2F1

After reset (0000)H

This register is read only.

When this register is read by the microprocessor, this register is reset (0000)H.

F0/15 : FAULT0/15

Number of faults detected by the Pseudo Random Sequence analyzer if the analyzer has been

validated and has recovered the receive sequence.

When the Fault Counter Register reaches (FFFF)H it stays at its maximum value.

VIII.11 - Time Slot Assigner Address Register - TAAR (14)H

bit15

bit8

bit7

bit 0

TS4

TS3

TS2

TS1

TS0

READ

HDI

After reset (0100)H

READ : READ MEMORY

READ = 1, Read Time slot Assigner Memory.

READ = 0, Write Time slot Assigner Memory.

TS0/4 : TIME SLOTS0/4

These five bits define one of 32 time slots in which a channel is set-up or not.

HDI

: HDLC INIT

HDI = 1, TSA Memory, Tx HDLC, Tx DMA, Rx HDLC, Rx DMA and GCI controllers are reset

within 250ms. An automate writes data from Time slot Assigner Data Register (TADR) (except

CH0/4 bits) into each TSA Memory location. If the microprocessor reads Time slot Assigner

Memory after HDLC INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4

bits of Time slot Assigner Address Register.

HDI = 0, Normal state.

N.B.

After software reset (bit 2 of IDCR Register) or pin reset the automate above-mentioned is working.

The automate is stopped when the microprocessor writes TAAR Register with HDI = 0.

VIII - INTERNAL REGISTERS (continued)

STLC5464

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