STLC5464 datasheet(66/83 Pages) STMICROELECTRONICS

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VIII.16 - Address Field Recognition Data Register - AFRDR (1E)H

bit15

bit8

bit7

bit 0

AF15

AF14 AF13

AF12 AF11

AF10

AF9

AF8

AF7

AF6

AF5

AF4

AF3

AF2

AF1

AF0

After reset (0001)H

AF0/15 : ADDRESS FIELD BITS

AF0/7 ; First byte received; AF8/15: Second byte received.

These two bytes are stored into Address Field Recognition Memory when AFRAR is written by

the microprocessor.

VIII.17 - Fill Character Register - FCR (20)H

bit15

bit8

bit7

bit 0

FC7

FC6

FC5

FC4

FC3

FC2

FC1

FC0

After reset (0000)H

FC0/7 : FILL CHARACTER (eight bits)

In Transparent Mode M1, twomessages are separatedby FILLCHARACTERS andthe detection

of one FILL CHARACTER marks the end of a message.

VIII.18 - GCI Channels Definition Register 0 - GCIR0 (22)H

The definitions of x and y indices are the same for GCIR0, GCIR1, GCIR2, GCIR3 :

-0

≤ x ≤ 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5

- y = 0, TDM4 is selected

- y = 1, TDM5 is selected.

bit15

bit8

bit7

bit 0

ANA11 VCI11 V*11 VM11 ANA10 VCI10 V*10 VM10 ANA01 VCI01 V*01 VM01 ANA00 VCI00 V*00 VM00

TDM5

TDM4

TDM5

TDM4

GCI CHANNEL 1

GCI CHANNEL 0

After reset (0000)H

VMxy

: VALIDATION of MONITOR CHANNELx, MULTIPLEX y :

When this bit is at 1, monitor channel xy is validated.

When this bit is at 0, monitor channel xy is not validated.

On line to reset (if necessary) one MON channel which had been selected previously VMxy must

be put at 0 during 125ms before reselecting this channel. Deselecting one MON channel during

125ms resets this MON channel.

V*xy

: VALIDATION of V Starx, MULTIPLEX y

When this bit is at 1, V Star protocol is validated if VMxy=1.

When this bit is at 0, GCI Monitor protocol is validated if VMxy=1.

VCxy

: VALIDATION of Command/Indicate CHANNEL x, MULTIPLEXy

When this bit is at 1, Command/Indicate channelxy is validated.

When this bit is at 0, Command/Indicate channelxy is not validated.

It is necessary to let VCxy at ”0” during 125ms to initiate the Command/Indicate channel.

ANAxy : ANALOG APPLICATION

When this bit is at 1, Primitive has 6 bits if C/Ixy is validated.

When this bit is at 0, Primitive has 4 bits if C/Ixy is validated.

VIII - INTERNAL REGISTERS (continued)

STLC5464

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