STLC5464 datasheet(11/83 Pages) STMICROELECTRONICS

11 / 83 page

I.2 - Pin Description (continued)

Pin N

Symbol

Type

Function

MICROPROCESSOR INTERFACE (continued)

NLDS

Lower Data Strobe (68000)

NUDS

Bus High Enable (Intel) / Upper Data Strobe (68000)

NDTACK

O8D

Data Transfer Acknowledge (68000)

READY

O8T

Data Transfer Acknowledge (Intel)

NAS/ALE

Address Strobe(Motorola) / Addresss Latch Enable(Intel)

R/W / NWR

Read/Write (Motorola) / Write(Intel)

NDS/NRD

Data Strobe (Motorola) /Read Data (Intel)

A0/AD0

I/O

Address bit 0 (Motorola) / Address/Data bit 0 (Intel)

A1/AD1

I/O

Address bit 1 (Motorola) / Address/Data bit 1 (Intel)

A2/AD2

I/O

Address bit 2 (Motorola) / Address/Data bit 2 (Intel)

A3/AD3

I/O

Address bit 3 (Motorola) / Address/Data bit 3 (Intel)

A4/AD4

I/O

Address bit 4 (Motorola) / Address/Data bit 4 (Intel)

A5/AD5

I/O

Address bit 5 (Motorola) / Address/Data bit 5 (Intel)

A6/AD6

I/O

Address bit 6 (Motorola) / Address/Data bit 6 (Intel)

A7/AD7

I/O

Address bit 7 (Motorola) / Address/Data bit 7 (Intel)

A8/AD8

I/O

Address bit 8 (Motorola) / Address/Data bit 8 (Intel)

A9/AD9

I/O

Address bit 9 (Motorola) / Address/Data bit 9 (Intel)

A10/AD10

I/O

Address bit 10 (Motorola) / Address/Data bit 10 (Intel)

A11/AD11

I/O

Address bit 11 (Motorola) / Address/Data bit 11 (Intel)

A12/AD12

I/O

Address bit 12 (Motorola) / Address/Data bit 12 (Intel)

A13/AD13

I/O

Address bit 13 (Motorola) / Address/Data bit 13 (Intel)

A14/AD14

I/O

Address bit14 (Motorola) / Address/Data bit 14 (Intel)

A15/AD15

I/O

Address bit15 (Motorola) / Address/Data bit 15 (Intel)

A16

Address bit16 (Motorola) / Address bit 16 (Intel)

A17

Address bit17 (Motorola) / Address bit 17 (Intel)

A18

Address bit18 (Motorola) / Address bit 18 (Intel)

A19

Address bit19 (Motorola) / Address bit 19 (Intel)

A20/ADM15

I/O

Address bit 20 from

µP (input) / Address bit 15 for SRAM (output)

A21/ADM16

I/O

Address bit 21 from

µP (input) / Address bit 16 for SRAM (output)

A22/ADM17

I/O

Address bit 22 from

µP (input) / Address bit 17 for SRAM (output)

A23/ADM18

I/O

Address bit 23 from

µP (input) / Address bit 18 for SRAM (output)

I/O

Data bit 0 for

µP if not multiplexed (see Note 1).

I/O

Data bit 1 for

µP if not multiplexed

I/O

Data bit 2 for

µP if not multiplexed

I/O

Data bit 3 for

µP if not multiplexed

I/O

Data bit 4 for

µP if not multiplexed

I/O

Data bit 5 for

µP if not multiplexed

I/O

Data bit 6 for

µP if not multiplexed

I/O

Data bit 7 for

µP if not multiplexed

I/O

Data bit 8 for

µP if not multiplexed

Type : I1 = Input TTL ;

I2 = I1 + Pull-up ;

I3 = I1 + Hysteresis ;

I4 = I3 + Pull-up ;

O4 = Output CMOS 4mA ;

O4T = O4 + Tristate ;

O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;

O8D = Output CMOS 8mA, Open Drain ;

O8DT = Output CMOS 8mA, Open Drain or Tristate ;

O8T = Output CMOS 8mA, Tristate

I - PIN INFORMATION (continued)

STLC5464

11/83

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