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STLC5464 Fiches technique(PDF) 41 Page - STMicroelectronics |
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STLC5464 Fiches technique(HTML) 41 Page - STMicroelectronics |
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41 / 83 page ![]() V - CLOCK TIMING (continued) V.4 - V* Interface CH0 CH1 CH7 B1 B2 MON D C/I AT 125 µs t1 t3 Bit 3, Time S lot 31 t3 t7 t7 FS re ce ived by th e Multi-HDLC DIN4/5 DOUT4/5 DCLK de livere d by th e Multi-HDLC FSCV* de live re d by th e Multi-HDLC DOUT0/7, CB if FSCG is conne cte d to FS DIN0/8 Th e four Multiple x Configura tion Re giste rs a re a t z e ro (no de la y be twe e n FS a nd Multiple xe s ). GCI Ch a nn e l Figure 30 : V* Synchronization Signal delivered by the Multi-HDLC Symbol Parameter Min. Typ. Max. Unit t1 Clock Period 4096kHz 244 ns t3 DCLK to FSCV* 20 ns t5 Duration FSCV* 244 ns t6 Clock to Data 50pF Clock to Data 100pF 50 100 ns nS t7 Set-up Time Data/DCLK 20 ns t7 Hold Time Data/DCLK 20 ns STLC5464 41/83 |
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