STLC5464 datasheet(68/83 Pages) STMICROELECTRONICS

68 / 83 page

VIII.22 - Transmit Command / Indicate Register - TCIR (2A)H

bit15

bit8

bit7

bit 0

CA2

CA1

CA0

READ

After reset (00FF)H

When this register is written by the microprocessor, these different bits mean :

READ : READ C/I MEMORY

READ = 1, READ C/I MEMORY.

READ = 0, WRITE C/I MEMORY.

CA 0/2 : TRANSMIT COMMAND/INDICATE MEMORY ADDRESS

CA 0/2 : These bits define one of eight Command/Indicate Channels.

: This bit defines one of two GCI multiplexes.

G0 = 0, TDM4 is selected.

G0 = 1, TDM5 is selected.

C6/1

: New Primitive to be transmitted

C6 is transmitted first if ANA = 1.

C4 is transmitted first if ANA = 0.

The New Primitive is taken into account by the transmitter after writing bits 8 to 15 (if 8 bit microprocessor).

Transmit Command/Indicate Register (after reading)

bit15

bit8

bit7

bit 0

CA2

CA1

CA0

READ

PT1

PT0

When this register is read by the microprocessor, these different bits mean :

READ : READ C/I MEMORY

READ = 1, READ C/I MEMORY.

READ = 0, WRITE C/I MEMORY.

CA 0/2 : TRANSMIT C/I ADDRESS

CA 0/2 : These bits define one of eight Command/Indicate Channels.

: This bit defines one of two GCI multiplexes.

G0 = 0, TDM4 is selected.

G0 = 1, TDM5 is selected.

C6/1

: Last Primitive transmitted.

PT0/1 : Status bits

Primitive Status

Primitive has not been transmitted yet.

Primitive has been transmitted once.

Primitive has been transmitted twice.

Primitive has been transmitted three times or more.

VIII - INTERNAL REGISTERS (continued)

STLC5464

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