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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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DSP56303 Fiches technique(PDF) 92 Page - Freescale Semiconductor, Inc |
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DSP56303 Fiches technique(HTML) 92 Page - Freescale Semiconductor, Inc |
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92 / 292 page  DSP56303 User’s Manual, Rev. 2 4-34 Freescale Semiconductor Core Configuration 4.9 JTAG Identification (ID) Register The JTAG ID register is a 32-bit read-only factory-programmed register that distinguishes the component on a board according to the IEEE 1149.1 standard. Figure 4-11 shows the JTAG ID register configuration. Version information corresponds to the revision number ($0 for revision 0, $1 for revision A, and so forth). I) 4.10 JTAG Boundary Scan Register (BSR) The BSR in the DSP56303 JTAG implementation contains bits for all device signals, clock pins, and their associated control signals. All bidirectional pins have a corresponding register bit in the BSR for pin data and are controlled by an associated control bit in the BSR. For details on the BSR, consult the DSP56300 Family Manual. For the latest description of the BSR contents by available package type in boundary scan description language (BSDL), call your local Freescale Semiconductor Sales Office or authorized distributor or visit the Freescale Semiconductor web site listed on the back cover of this manual. 31 28 27 22 21 12 11 1 0 Version Information Design Center Number Sequence Number Manufacturer Identity 1 0101 000110 0000000011 00000001110 1 Figure 4-11. JTAG Identification Register Configuration (Revision E) |
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