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HE847701

HE80000 SERIES

March 26, 2004

Page 23 of 29

V1.03

This specification is subject to change without notice. Please contact sales person for the latest version before use.

program can operate normally. When abnormal conditions happen to cause the MCU to divert from

normal path, the WDT counter will not be cleared and reset signal will be generated.

WDT is the enabling signal generated by calculating 32768-clock overflow. Reset Register content is

same as TC1 (Timer1 clock), which uses the same clock count source. WDT function can be generated in

Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1 clock has

stopped.)

15. Digital-to-Analog Converter

The Digital-to-Analog converter (DAC) converts the 7-bit unsigned speech data written to PWMC to

proportional current output.

PWMC register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DA & PWM Data

0

DA and PWM output value

Control

1

PWM O/P driver

-

-

-

PWME

There are two output paths for the DAC. Either VO or DAO can be selected as output port of DAC by

VOC register when it is enabled. The VO output is primarily intended for speech generation, although it

is not necessary so, while the DAO output path can be used in conjunction with built-in OP comparator to

function as an Analog-to-Digital Converter as required in applications such as speech recording, speech

recognition or sensor interfaces.

OPO

OPIP

OPIN

DAO

PWMC[DATA]

VO

VOC[DAC]

VOC[OP]

R

DAC

+

-

1

0

OP

The DAC is enabled by DAC bit of VOC register. Please note that the DAC bit of VOC register will be

automatically cleared when the system enter Idle or Sleep mode. So it needs to be set again when

returning to Normal mode.

VOC

VOC register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Initial

-

-

-

-

-

0

0

0

-

-

-

-

-

PWM

DAC

OP

Bit Name Value Function description

1

DAC

1

DA Enable