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HE847701

HE80000 SERIES

March 26, 2004

Page 20 of 29

V1.03

This specification is subject to change without notice. Please contact sales person for the latest version before use.

T1H

T1L

"Timer1 Counter"

decreases 1

Count TO

0xFFFFh

Auto reload when

Timer1 underflow

No

Start Timer1

Interrupt Request.

Yes

The contents of T1H and

T1L almost loaded into

Timer1 immediately

when Timer1 is turned on

after reset.

T1_INT

The Timer1 related control registers are list as below:

Register Address

Field

Bit position Mode

Description

IER

0x02

TC1_IER

2

R/W 0: TC1 interrupt is disabled. (default)

1: TC1 interrupt is enabled.

T1L

0x03

T1L[7:0]

7~0

W

Low byte of TC1 pre-load value

T1H

0x04

T1H[7:0]

7~0

W

High byte of TC1 pre-load value

OP1

0x09

TC1E

2

R/W 0: TC1 is disabled. (default)

1: TC1 is enabled.

12. Timer2

Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock

“Fsys”/1.5. The system clock “Fsys” varies depending on the operation modes of the MCU.

The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If

Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will

be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded