King Billion Electronics Co., Ltd

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HE847701

HE80000 SERIES

March 26, 2004

Page 4 of 29

V1.03

This specification is subject to change without notice. Please contact sales person for the latest version before use.

Pin Name

Pin # I/O

Description

will turn on the key scan function.

PRT14[7..0]

26 ~ 33

B/

O

8-bit bi-directional I/O port 14 is shared with LCD segment pads SEG[23..16]. The

function of the pad can be selected individually by mask options MO_LIO14[7..0].

(‘1’ for LCD and ‘0’ for I/O).

The output type of I/O pad can also be selected by mask option MO_14PP[7..0] (1

for push-pull and ‘0’ for open-drain).

As the output structure of I/O pad does not contain tri-state buffer. When using the

I/O as input, “1” must be outputted before reading.

PRT15[7..0]

34 ~ 41

B/

O

8-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[16..8]. The

function of the pad can be selected individually by mask options MO_LIO15[7..0].

(‘1’ for LCD and ‘0’ for I/O).

The output type of I/O pad can also be selected by mask option MO_15PP[7..0] (1

for push-pull and ‘0’ for open-drain).

As the output structure of I/O pad does not contain tri-state buffer. When using the

I/O as input, “1” must be outputted before reading.

PRT17[7..0]

42 ~ 49

B/

O

8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[7..0]. The

function of the pad can be selected individually by mask options MO_LIO17[7..0].

(‘1’ for LCD and ‘0’ for I/O).

The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1

for push-pull and ‘0’ for open-drain).

As the output structure of I/O pad does not contain tri-state buffer. When using the

I/O as input, “1” must be outputted before reading.

COM[31..0]

50 ~ 81 O LCD COMMON Driver pads.

LVL1

82

B LCD Bias Voltage 1

LVL2

83

B LCD Bias Voltage 2

LVL3

84

B LCD Bias Voltage 3

LVL4

85

B LCD Bias Voltage 4

LVL5

86

B LCD Bias Voltage 5

LCAP4A

87

B Charge Pump Capacitor Pin

LCAP4B

88

B Charge Pump Capacitor Pin.

LCAP3A

89

B Charge Pump Capacitor Pin

LCAP3B

90

B Charge Pump Capacitor Pin

LCAP2A

91

B Charge Pump Capacitor Pin

LCAP2B

92

B Charge Pump Capacitor Pin

LCAP1A

93

B Charge Pump Capacitor Pin

LCAP1B

94

B Charge Pump Capacitor Pin

LCDGS

95

B LCD Voltage setting. Adjust Resistor between LCDGS and LVL2 to set LVL5.

LCDVX

96

B Charge Pump Capacitor Pin

LCDVTB

97

B Charge Pump Capacitor Pin

LFR

98

O LCD frame signal for interfacing with LCD segment extender KD80.

LDL

99

O LCD data load pin for interfacing with LCD segment extender KD80.

GND

100

P

Power ground Input.

VO

101

O

DAC Voice Output. Set the bit 1 and clear the bit 0 of VOC (DA = ‘1’ and OP = ‘0’)

register to turn on DAC with VO output.

DAO

102

O

Alternate output of DAC. Set both bit 1 and bit 0 of VOC register (DA = ‘1’ and OP

= ‘1’) to turn on DAC with DAO output as well as OP comparator.

OPIN

103

I

Inverting input of OP Amp. Set the bit 0 of VOC register (OP = ‘1’) to turn on OP

comparator.

OPIP

104

I

Non-inverting input of OP Amp.

OPO

105

O Output of OP Amp.

RSTP_N

106

I

System Reset input pin. Level trigger, active low on this pin will put the chip in reset

state.