SPEAR600 datasheet(41/97 Pages) STMICROELECTRONICS

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SPEAr600

Pin description

Doc ID 16259 Rev 3

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3.3

Configuration modes

The previous tables show the connectivity of the pins in the default configuration mode (full

features). On top of this SPEAr600 can be also configured in different modes.

This section describes the main operating modes created by disabling some IPs to enable

other ones.

The following modes can be selected by setting the TEST_0 .. TEST_5 pins at the

appropriate values. This setting is used to program the control register (SOC_CFG_CTR)

present in the Miscellaneous registers block (MISC). Please refer to the section 11.4.3 of the

SPEAr600 reference manual (RM0305)

●

Mode 0: Full features

●

Mode 1: Disable_nand_flash

●

Mode 2: Disable_LCD_ctr

●

Mode 3: Disable_GMAC_ctr

●

Mode 4: self_cfg4

●

Mode 5: self_cfg5

●

Mode6: Full RAS

●

Mode7: All_Process_disable

Table 16: Multiplexing scheme shows all the alternate functions available in each mode.

Mode 0 is the default mode for SPEAr600.

3.3.1

Full features

Default configuration, I/O standard features.

3.3.2

Disable NAND Flash

The NAND Flash interface is disabled and alternatively the following features are provided:

●

UART extension for modem flow control

●

One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user

manual for more details).

3.3.3

Disable LCD ctr

The Color LCD controller interface is disabled and alternatively the following features are

provided:

●

UART extension for modem flow control

●

One additional clock programmable trought GPT registers. Please refer to the

SPEAr600 user manual (UM0510) for more details.

●

Additional 8 data lines of NAND Flash interface not otherwise available.

●

One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user

manual for more details).

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