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SPEAR600 Fiches technique(PDF) 23 Page - STMicroelectronics |
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SPEAR600 Fiches technique(HTML) 23 Page - STMicroelectronics |
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23 / 97 page ![]() SPEAr600 Architecture overview Doc ID 16259 Rev 3 23/97 – 4 dual port memory cuts (1024 words x 32 bits) ● Clock system constituted by: – 5 clocks coming from the external balls – 4 clocks coming from the integrated frequency synthesizers – CPU core clock frequency – Pll2 frequency – 48 MHz clock (USB Pll) – 30 MHz clock (Main Oscillator) – 32.768 kHz clock (RTC Oscillator) – APB clock (programmable) – AHB clock (programmable) – User Configurable sync/async clock towards Memory Controller port 2 (M2) ● Connection with 84/112 I/Os ● Connection with 9 LVDS lines ● 12 interrupt lines towards CPU1 and CPU2 ● 64 interrupt input lines from the various platform IP sources ● 16 peripheral DMA request lines ● 64 user configurable (in the SoC) general purpose input lines ● 64 user configurable (in the RAS) general purpose output lines ● SoC dynamic power management control interface; ● 50 specific ATE Test interface signals dedicated to RAS 2.25 External Port Controller (EXPI I/F) The port controller is a socket communication interface between the SPEAr600 and an external FPGA device; it implements a simple AHB bidirectional protocol used to compress a couple of std AHB master/slave bus onto 84 PL_GPIOs and 4 PL_CLK primary signals. Caution: PL_GPIO pins are not configurable by software. ST provide a symmetric port controller logic solution to be embedded inside the external FPGA with the purpose of interfacing the EXPI bus directly and decompressing the same pair of AHB master/slave ports on the FPGA side in order to interconnect the customer logic as follows (more slave and master agents can be connected to the EXPI): SPEAr600_AHB-master >> FPGA_AHB-slave SPEAr600_AHB-slave << FPGA_AHB-master (AHB-full) The EXPI interface is based on two main groups of signals: ● AHB bidirectional signal bus driven alternatively from the SPEAr600 and FPGA side. ● Unidirectional signals continuously driven from both the SPEAr600 and FPGA sides. Table 36: EXPI - pad signal assignment lists the EXPI signal names. Further details in these signals are given in the SPEAr600 user manual (UM0510) |
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