SPEAR600 datasheet(20/97 Pages) STMICROELECTRONICS

20 / 97 page

Architecture overview

SPEAr600

20/97

Doc ID 16259 Rev 3

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Reset status capture and soft reset generation

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Watchdog module clock enable

2.18.1

Power saving system mode control

Using three mode control bits, the system controller switch the SPEAr600 to any one of four

different modes: DOZE, SLEEP, SLOW and NORMAL.

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SLEEP mode: In this mode the system clocks, HCLK and CLK, are disabled and the

System Controller clock SCLK is driven by a low speed oscillator (nominally 32768 Hz).

When either a FIQ or an IRQ interrupt is generated (through the VIC) the system enters

DOZE mode. Additionally, the operating mode setting in the system control register

automatically changes from SLEEP to DOZE.

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DOZE mode: In this mode the system clocks, HCLK and CLK, and the System

Controller clock SCLK are driven by a low speed oscillator. The System Controller

moves into SLEEP mode from DOZE mode only when none of the mode control bits

are set and the processor is in Wait-for-interrupt state. If SLOW mode or NORMAL

mode is required the system moves into the XTAL control transition state to initialize the

crystal oscillator.

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SLOW mode: During this mode, both the system clocks and the System Controller

clock are driven by the crystal oscillator. If NORMAL mode is selected, the system goes

into the "PLL control" transition state. If neither the SLOW nor the NORMAL mode

control bits are set, the system goes into the "Switch from XTAL" transition state.

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NORMAL mode: In NORMAL mode, both the system clocks and the System Controller

clock are driven by the PLL output. If the NORMAL mode control bit is not set, then the

system goes into the "Switch from PLL" transition state.

2.19

Clock and reset system

The clock system is a fully programmable block that generates all the clocks for the

SPEAr600.

The default operating clock frequencies are:

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Clock @ 333 MHz for the CPUs.

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Clock @ 166 MHz for AHB bus and AHB peripherals. (PLL1 source)

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Clock @ 83 MHz for, APB bus and APB peripherals. (PLL1 source)

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Clock @ 100-333 MHz for DDR memory interface. (PLL1, PLL2 source)

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Clock @ 12 MHz, 30 MHz and 48 MHz for USBs (PLL3 source)

The above frequencies are the maximum allowed values.

All these clocks are generated by three PLLs.

PLL1 and PLL2 sources are fully programmable through dedicated registers.

The clock system consists of 2 main parts: a multi clock generator block and two internal

PLLs.

The multi clock generator block, takes a reference signal (which is usually delivered by the

PLL), generates all clocks for the IPs of SPEAr600 according to dedicated programmable

registers.

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