SI4463 datasheet(44/53 Pages) SILABS

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Si4463/61/60-C

Rev 1.0

11. Pin Descriptions: Si4463/61/60

Pin Name

I/0

Description

1SDN

Shutdown Input Pin

0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode.

When SDN = 1, the chip will be completely shut down, and the contents of the

registers will be lost.

2RXp

Differential RF Input Pins of the LNA.

See application schematic for example matching network.

3RXn

4TX

Transmit Output Pin.

The PA output is an open-drain connection, so the L-C match must supply

VDD (+3.3 VDC nominal) to this pin.

5NC

It is recommended to connect this pin to GND per the reference design sche-

matic. Not connected internally to any circuitry.

6VDD

VDD

+1.8 to +3.8 V Supply Voltage Input to Internal Regulators.

The recommended VDD supply voltage is +3.3 V.

TXRAMP

Programmable Bias Output with Ramp Capability for External FET PA.

See "5.4. Transmitter (TX)" on page 33.

8VDD

VDD

+1.8 to +3.8 V Supply Voltage Input to Internal Regulators.

The recommended VDD supply voltage is +3.3 V.

GPIO0

I/O

General Purpose Digital I/O.

May be configured through the registers to perform various functions including:

Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery

Detect, TRSW, AntDiversity control, etc.

GPIO1

I/O

nIRQ

General Microcontroller Interrupt Status Output.

When the Si4463/61 exhibits any one of the interrupt events, the nIRQ pin will

be set low = 0. The Microcontroller can then determine the state of the inter-

rupt by reading the interrupt status. No external resistor pull-up is required, but

it may be desirable if multiple interrupt lines are connected.

GND

PAD

15 nSEL

SDI

SDO

SCLK

SDN

nIRQ

RXp

RXn

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