SI4463 datasheet(7/53 Pages) SILABS

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Si4463/61/60-C

Rev 1.0

RX Sensitivity

915/868 MHz3

PRX_0.5

(BER < 0.1%)

(500 bps, GFSK, BT = 0.5,

f= 250Hz)

—–127—

dBm

PRX_40

(BER < 0.1%)

(40 kbps, GFSK, BT = 0.5,

f= 20 kHz)

—

–109

–107

dBm

PRX_100

(BER < 0.1%)

(100 kbps, GFSK, BT = 0.5,

f= 50 kHz)

—

–104

–102

dBm

PRX_500

(BER < 0.1%)

(500 kbps, GFSK, BT = 0.5,

f= 250 kHz)

—

–97

–92

dBm

PRX_9.6

(PER 1%)

(9.6 kbps, 4GFSK, BT = 0.5,

f=  kHz)

—–109—

dBm

PRX_1M

(PER 1%)

(1 Mbps, 4GFSK, BT = 0.5,

inner deviation = 83.3 kHz)

—

–88

—

dBm

PRX_OOK

(BER < 0.1%, 4.8 kbps, 350 kHz BW,

OOK, PN15 data)

—

–108

–104

dBm

(BER < 0.1%, 40 kbps, 350 kHz BW,

OOK, PN15 data)

—

–101

–97

dBm

(BER < 0.1%, 120 kbps, 350 kHz BW,

OOK, PN15 data)

—

–96

–91

dBm

RX Channel Bandwidth

1.1

—

850

kHz

RSSI Resolution

RESRSSI

Valid from –110 dBm to –90 dBm

—

±0.5

—

1-Ch Offset Selectivity,

169 MHz3

C/I1-CH

Desired Ref Signal 3 dB above sensitiv-

ity, BER < 0.1%. Interferer is CW, and

desired is modulated with 2.4 kbps

F = 1.2 kHz GFSK with BT = 0.5, RX

channel BW = 4.8 kHz,

channel spacing = 12.5 kHz

—

–69

–59

1-Ch Offset Selectivity,

450 MHz3

C/I1-CH

—

–60

–50

1-Ch Offset Selectivity,

868 / 915 MHz3

C/I1-CH

—

–55

–45

Blocking 1 MHz Offset

1MBLOCK Desired Ref Signal 3 dB above sensitiv-

ity, BER = 0.1%. Interferer is CW, and

desired is modulated with 2.4 kbps,

F = 1.2 kHz GFSK with BT = 0.5,

RX channel BW = 4.8 kHz

—

–79

–68

Blocking 8 MHz Offset

8MBLOCK

—

–86

–75

Table 3. Receiver AC Electrical Characteristics1,2 (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and

from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.

For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used.

Measured over 50000 bits using PN9 data sequence and data and clock on GPIOs. Sensitivity is expected to be better

if reading data from packet handler FIFO especially at higher data rates.

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