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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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STA321 Fiches technique(PDF) 59 Page - STMicroelectronics |
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STA321 Fiches technique(HTML) 59 Page - STMicroelectronics |
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59 / 157 page  STA321 FFX Doc ID 15351 Rev 3 59/157 7.8 PWM00 output Pin PWM00 is an additional output with a maximum driving capability of 2 mA to control an external bridge or external operational amplifier. By default, PWM00 is tied to logical 0. When register bit CKOCFG[0] is set to 1 then any FFX PWM channel output can be mapped to it. When the CMOS bridge is in standby the output PWM00 is, by default, turned off. However, it is possible to have the FFX signal PWM3A as the PWM00 output by using bit 3 of register FFXCFG0 on page 82, and this whatever the status of power-down or the 3-state signals of both bridges, even if they are different from the normal operating mode where the output is 0 when in power-down or 3-state mode. |
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