L99MH98 datasheet(31/147 Pages) STMICROELECTRONICS

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4.2.2

Vds measurement

The L99MH98 is able to reflect the drain to source voltage across each of the external MOSFETs with some gain

on one of the two CSOx pins. This is done for both the low and high side MOSFETs using an analog multiplexer.

This allows the user, through SPI, to select and monitor the drain to source voltage on any MOSFET for the

purpose of load current estimation. The selected drain source voltage is reflected on the CSOx pin when the

MOSFET is fully on. To do this, the CSOx pins are tri-stated when the selected MOSFET is OFF and enabled,

after some dead time, when the MOSFET is ON. This allows a small capacitor on the CSOx pin to sustain the

amplified drain to source voltage for reliable conversion by the ADC of the microcontroller.

The CSO1 and CSO2 outputs can be enabled/disabled by the CSOENx, x = 1...2, registers. In case of disable the

output is in high impedance.

The Vds of all 16 MOSFETs connected to L99MH98 can be measured. To map one of the Vds to one of the two

CSOx, the two CSOSIGx, x = 1...2, and CSOSHx, x = 1...2, registers must be used (see the Table 25).

To read the Vds voltage the device uses internal current sense amplifiers circuits. In this way, the L99MH98 can

reflect the drain to source voltage across each of the external MOSFETs, with a gain on one of the two CSOx

pins. This is possible for both low and high side MOSFETs using an analog multiplexer. The error of the selected

gain is included in the total error parameter.

The total gain of the CSOx is composed by the contribution of two different stages:

•

The gain of the first stage is related to the drain-source monitoring thresholds of the used MOSFET

(VDS_CONFx bits). By setting the drain-source monitoring threshold to 75 mV (VDS_CONFx = 0000) or

150 mV (VDS_CONFx = 0001), the gain of the first stage will be set to 10 [V/V]. For drain-source

monitoring thresholds from 200 mV (VDS_CONFx = 0010) to 400 mV (VDS_CONFx = 0101), however, the

gain of the first stage is set to 2.5 V/V.

•

The second stage gain, on the other hand, is controlled by a bit for each CSO channel, CSO_GAIN_SELx

to the single CSO channel. When CSO_GAIN_SEL = 0 the gain set is 1.5 V/V, when CSO_GAIN_SEL = 1

is 3 V/V.

The total gain is, therefore, given by the product of the two selected gains.

The choice of the gains will be made according to the output voltage of the CSOx. Since the validity of the output

of the CSOx is granted if its value is in the range between 0.1 V and VDD-0.3 V, the gains to choose must be set

to obtain a compatible CSO output value (approximately in the middle of this range), starting from the considered

input value of Vds.

Table 25. Vds mapping on CSO1 and CSO2

CSOSIGx

CSOSHx

Setting

000

Vds of the HS1 mapped on the CSOx

001

Vds of the HS2 mapped on the CSOx

010

Vds of the HS3 mapped on the CSOx

011

Vds of the HS4 mapped on the CSOx

100

Vds of the HS5 mapped on the CSOx

101

Vds of the HS6 mapped on the CSOx

110

Vds of the HS7 mapped on the CSOx

111

Vds of the HS8 mapped on the CSOx

000

Vds of the LS1 mapped on the CSOx

001

Vds of the LS2 mapped on the CSOx

010

Vds of the LS3 mapped on the CSOx

011

Vds of the LS4 mapped on the CSOx

100

Vds of the LS5 mapped on the CSOx

101

Vds of the LS6 mapped on the CSOx

110

Vds of the LS7 mapped on the CSOx

L99MH98

Gates driver

DS14611 - Rev 3

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