L99MH98 datasheet(44/147 Pages) STMICROELECTRONICS

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The logic level signal at the pin is the logical NOR combination of all the status flags and status bits linked to the

pin through the DIAGCR1 and DIAGCR2 control registers, together with the global status byte RSTB bit.

Once the device comes out of reset mode, the DIAGN pin is pulled low because of the global status byte RSTB

bit. In case that just the global status byte RSTB bit is set, any valid SPI communication frame clears the RSTB bit

pulling up the DIAGN pin. Any read access to the DSR1 and DSR2 registers reset this signal to a high level, until

an error coming from a new source occurs again by pulling the pin low.

DIAGN pin is active low as default, but it is possible to change its functionality by the DIAGN_ACTIVE_LEVEL bit:

setting this bit to one the DIAGN pin will be active high.

If a fault coming from a new error source occurs during the read access to the DSR1 and DSR2 registers, the

DIAGN output pin remains low (this avoids any loss of information since the new error source status flag/bit will

not be reported by the concomitant read access, but a new read access would be required).

Even if a read operation of the status register should always come before a “read and clear” operation: any “read

and clear” operation of status registers DSR1 and DSR2 will pull the DIAGN pin high.

5.8

Configurable window watchdog

Out of reset mode, the L99MH98 watchdog monitors the microcontroller status within a periodic window. By

default, as soon as the device finishes the powerup phase, the watchdog is enabled and starts running with a long

open window. The long open window provides more time to the microcontroller for the L99MH98 initialization and

allows the watchdog disabling procedure to be run when no watchdog is required by the application.

To trigger the watchdog for the first time during a LOW (long open window), the microcontroller must write 5555h

to the watchdog trigger/disable register (WDGTRDIS) before the end of the long open window.

After the first valid watchdog trigger, the watchdog will enter in window mode. In window mode the microcontroller

has to serve the watchdog by alternating the watchdog trigger bits (that is, 2AAAh,5555h,…) of the watchdog

trigger/disable register (WDGTRDIS) within the watchdog open window. Any correct watchdog trigger SPI frame

will immediately start a new window.

In case of a watchdog failure, because of any watchdog trigger outside the open window, invalid or unexpected

watchdog trigger bits value, any watchdog timeout, any disabling procedure out of the LOW or any wrong

disabling procedure during the LOW will set the WDG_ERROR flag, stop the watchdog and put the device in fail-

safe mode. In fail-safe mode the OUTEx control bits are reset, and the gate drivers are forced to switch off

actively all the MOSFETs with the maximum available current, regardless of the programmed gate discharge

current. To reactivate the gate drivers that are forced in disabled mode, the WDG_ERROR flag must be cleared

via SPI (clearing the WDG_ERROR flag makes the device come out of the fail-safe mode and makes the

watchdog start again with a long open window) and then the OUTEx control bits must be set to one via SPI. As

long as the device is in fail-safe mode (WDG_ERROR = 1), the OUTEx control bits are reset and cannot be set

via SPI.

Once the watchdog starts running again with a long open window after coming out of the fail-safe mode, to enter

in window mode the microcontroller must write 5555h to the watchdog trigger/disable register (WDGTRDIS).

To disable the watchdog, the microcontroller must write a specific key, consisting in two consecutive valid SPI

frames to be sent in the right order (2F6Bh first key word, 1097h second key word), to control register

WDGTRDIS, within a window (ttimeout). To enable the watchdog, the microcontroller must write a specific key,

consisting in two consecutive valid SPI frames to be sent in the right order (5C99h first key word, 4360h second

key word), to control register WDGTRDIST, within a window (ttimeout).

Any other SPI transfer between the two SPI frames carrying the key, including an invalid SPI transfer, will abort

the disabled process and generate a watchdog fault (WDG_ERROR). Besides, the keys sent in the wrong order

will not disable the watchdog and generate a watchdog fault as well.

Any read access to the WDGTRDIS register provides information concerning the watchdog disabling procedure

result together with the three least significant bits of the latest write operation performed on the same register.

L99MH98

Protections and diagnostics

DS14611 - Rev 3

page 44/147

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