L99MH98 datasheet(46/147 Pages) STMICROELECTRONICS

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Serial peripheral interface (SPI)

A 24-bit SPI is used for bidirectional communication with the microcontroller.

The microcontroller SPI peripheral must run in the following configuration:

•

CPOL = 0

•

CPHA = 1

In this configuration the input data from the SDI pin is sampled by the high to low transition of the serial clock

CLK, and the output data is changed by the low to high transition of the serial clock CLK.

The correct reception of any SPI frame is not guaranteed during a tSTART time after the enable pin goes high with

the VDD supply already ON.

The SPI protocol implemented in L99MH98 is an out-of-frame: the IC provides on the frame n+1 the content of the

reading request on the frame n.

Note:

The SPI bus can be used in a parallel configuration by controlling the CSN signal of the connected IC’s.

It is advisable to read the global status SPI registers after the power-up in order to clear the diagnostic.

Chip select not (CSN)

The CSN input pin is used to address the SPI communication with the device. When CSN is high, the output pin

(SDO) is in high impedance. When CSN is low, the output pin (SDO) driver is enabled, and a serial

communication can start. The information transferred during CSN = 0 is called a communication frame. When

CSN = high for t > t9 the SDO output is switched into high impedance to allow SPI communications with other SPI

nodes.

Serial data in (SDI)

The SDI input pin is used to transfer data into the device. The data applied to the SDI will be sampled on the

falling edge of the serial CLK signal and shifted into an internal 24-bit shift register. At the rising edge of the CSN

signal the content of the shift register will be transferred to the data input register. The writing to the selected data

input register is enabled only if exactly 24 bits are transmitted within one communication frame (that is, CSN low).

Instead, the writing to the selected data input register is not enabled if one of the following cases happens:

•

More or less than 24 clock pulses are counted within one frame

•

During the falling and rising edge of CSN the level of SCLK is not low

•

All bits of a command received at SDI are logic 0 or logic 1

•

The number of CKL rising edges in a frame is not 24

•

The address field is unknown

•

The parity check fails

This safety function is implemented to avoid an activation of the output stages by any wrong communication

frame.

Serial data out (SDO)

The SDO output driver is activated by a logical low level at the CSN input and will go from high impedance to low

or high level depending on the global error flag value (GSBN bit). The first rising edge of the CLK input after a

high to low transition of the CSN pin will transfer the “SPI error or RESET” bit and, immediately after, the global

status byte bit out. Each subsequent rising edge of the CLK shifts the following bits out.

Serial clock (CLK)

The CLK input pin is used to synchronize the input and output serial bit streams. The data input (SDI) is sampled

on the falling edge of the CLK and the data output (SDO) will change on the rising edge of the CLK. The SPI can

work with a CLK frequency up to 6 MHz.

6.1

Physical layer

This chapter describes the SPI protocol configuration. It defines a common structure of the communication frames

and defines specific addresses for product and status information.

The ST-SPI allows usage of generic software to operate the devices while maintaining the required flexibility to

adapt it to the individual functionality of a particular product. In addition, fail-safe mechanisms are implemented to

protect the communication from external influences and wrong or unwanted usage.

The SPI connection between the microcontroller and the L99MH98 is shown in the Figure 31.

L99MH98

Serial peripheral interface (SPI)

DS14611 - Rev 3

page 46/147

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