ST10F269Z1Q6 datasheet(16/184 Pages) STMICROELECTRONICS

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4 - MEMORY ORGANIZATION

ST10F269

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XPERCON (F024h / 12h)

ESFR

Reset Value: - - 05h

Note: - When both CAN are disabled via XPER-

CON setting, then any access in the

address range 00’EE00h - 00’EFFFh will

be directed to external memory interface,

using the BUSCONx register correspond-

ing to address matching ADDRSELx regis-

ter. P4.4 and P4.7 can be used as General

Purpose I/O when CAN2 is disabled, and

P4.5 and P4.6 can be used as General

Purpose I/O when CAN1 is disabled.

- The default XPER selection after Reset is

identical

XBUS

configuration

ST10C167: XCAN1 is enabled, XCAN2 is

disabled, XRAM1 (2K Byte compatible

XRAM) is enabled, XRAM2 (new 8K Byte

XRAM) is disabled.

- Register XPERCON cannot be changed

after the global enabling of XPeripherals,

i.e. after the setting of bit XPEN in the

SYSCON register.

- In EMUlation mode, all the XPERipherals

are enabled (XPERCON bit are all set).

The access to external memory and/or

XBus is controlled by the bondout chip.

- When the Real Time Clock is disabled

(RTCEN = 0), the clock oscillator is

switch-off

the

ST10

enters

power-down mode. Otherwise, when the

Real Time Clock is enabled, the bit

RTCOFF of the RTCCON register allows

to choose the power-down mode of the

clock oscillator (See Chapter : Real Time

Clock on page 105).

---

RTCEN

XRAM2EN

XRAM1EN

CAN2EN

CAN1EN

CAN1 Enable Bit

‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be

used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if

CAN2EN is also ‘0’.

‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.

CAN2EN

CAN2 Enable Bit

‘0’: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled. P4.4 and P4.7 pins can be

used as general purpose I/Os. Address range 00’EE00h-00’EEFFh is only directed to external memory if

CAN1EN is also ‘0’.

‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.

XRAM1EN

XRAM1 Enable Bit

‘0’: Accesses to external memory within space 00’E000h to 00’E7FFh. The 2K Bytes of internal XRAM1

are disabled.

’1’: Accesses to the internal 2K Bytes of XRAM1.

XRAM2EN

XRAM2 Enable Bit

‘0’: Accesses to the external memory within space 00’C000h to 00’DFFFh. The 8K Bytes of internal

XRAM2 are disabled.

’1’: Accesses to the internal 8K Bytes of XRAM2.

RTCEN

RTC Enable Bit

’0’: Accesses to the on-chip Real Time Clock are disabled, external access is performed. Address range

00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and CAN2EN are ’0’ also

’1’: The on-chip Real Time Clock is enabled and can be accessed.

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