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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST10F269Z1Q6 Fiches technique(PDF) 68 Page - STMicroelectronics |
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ST10F269Z1Q6 Fiches technique(HTML) 68 Page - STMicroelectronics |
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68 / 184 page  12 - PARALLEL PORTS ST10F269 68/184 12.5 - Port 2 If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP2. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP2. P2 (FFC0h / E0h) SFR Reset Value: 0000h DP2 (FFC2h / E1h) SFR Reset Value: 0000h ODP2 (F1C2h / E1h) ESFR Reset Value: 0000h 12.5.1 - Alternate Functions of Port 2 All Port 2 lines (P2.15...P2.0) serve as capture inputs or compare outputs (CC15IO...CC0IO) for the CAPCOM1 unit. When a Port 2 line is used as a capture input, the state of the input latch, which represents the state of the port pin, is directed to the CAPCOM unit via the line “Alternate Pin Data Input”. If an external capture trigger signal is used, the direction of the respective pin must be set to input. If the direction is set to output, the state of the port output latch will be read since the pin represents the state of the output latch. This can be used to trigger a capture event through software by setting or clearing the port latch. Note that in the output configuration, no external device may drive the pin, otherwise conflicts would occur. When a Port 2 line is used as a compare output (compare modes 1 and 3), the compare event (or the timer overflow in compare mode 3) directly effects the port output latch. In compare mode 1, when a valid compare match occurs, the state of the port output latch is read by the CAPCOM control hardware via the line “Alternate Latch Data Input”, inverted, and written back to the latch via the line “Alternate Data Output”. The port output latch is clocked by the signal “Compare Trigger” which is generated by the CAPCOM unit. In compare mode 3, when a match occurs, the value '1' is written to the port output latch via the line “Alternate Data Output”. When an overflow of the corresponding timer occurs, a '0' is written to the port output latch. In both cases, 15 14 13 12 11 10 98 765 432 10 P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW P2.y Port Data Register P2 Bit y 15 14 13 12 11 10 98 765 432 10 DP2 .15 DP2 .14 DP2 .13 DP2 .12 DP2 .11 DP2 .10 DP2 .9 DP2 .8 DP2 .7 DP2 .6 DP2 .5 DP2 .4 DP2 .3 DP2 .2 DP2 .1 DP2 .0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DP2.y Port Direction Register DP2 Bit y DP2.y = 0: Port line P2.y is an input (high-impedance) DP2.y = 1: Port line P2.y is an output 15 14 13 12 11 10 98 765 432 10 ODP2 .15 ODP2 .14 ODP2 .13 ODP2 .12 ODP2 .11 ODP2 .10 ODP2 .9 ODP2 .8 ODP2 .7 ODP2 .6 ODP2 .5 ODP2 .4 ODP2 .3 ODP2 .2 ODP2 .1 ODP2 .0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ODP2.y Port 2 Open Drain Control Register Bit y ODP2.y = 0: Port line P2.y output driver in push/pull mode ODP2.y = 1: Port line P2.y output driver in open drain mode |
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