PCF8811USLASH2DASLASH1 datasheet(23/73 Pages) PHILIPS

23 / 73 page

2004 May 17

Philips Semiconductors

Product speciﬁcation

× 128 pixels matrix LCD driver

PCF8811

handbook, full pagewidth

MBC602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

Fig.25 Acknowledge on the I2C-bus.

12.2

I2C-bus Hs-mode protocol

The PCF8811 is a slave receiver/transmitter. If data is to

be read from the device, the SDAH pin must be connected,

otherwise SDAH may be unused.

Hs-mode can only commence after the following

conditions:

• START condition (S)

• 8-bit master code (00001XXX)

• Not-acknowledge bit (A).

The master code has two functions: it allows arbitration

and synchronization between competing masters at

F/S-mode speeds, resulting in one winner. The master

code also indicates the beginning of an Hs-mode transfer.

These conditions are illustrated in Figs 26 and 27.

As no device is allowed to acknowledge the master code,

the master code is followed by a not-acknowledge (A).

After this A bit, and the SCLH line has been pulled up to

a HIGH level, the active master switches to Hs-mode and

enables at tH the current-source pull-up circuit for the

SCLH signal (see Fig.27).

The active master will then send a repeated START

condition (Sr) followed by a 7-bit slave address with a R/W

bit, and receives an acknowledge bit (A) from the selected

slave.

After each acknowledge bit (A) or not-acknowledge bit (A)

the active master disables its current source pull-up circuit.

The active master re-enables its current source again

when all devices have been released and the SCLH signal

reaches a HIGH level. The rising of the SCLH signal is

done by a pull-up resistor and therefore is slower, the last

part of the SCLH rise time is speeded up because the

current source is enabled. Data transfer only switches

back to F/S mode after a STOP condition (P).

A write sequence after the Hs-mode is selected is

illustrated in Fig.28. The sequence is initiated with

a START condition (S) from the I2C-bus master which is

followed by the slave address. All slaves with the

corresponding address acknowledge in parallel, the

remainder will ignore the I2C-bus transfer.

After the acknowledgement cycle of a write (W), one or

more command words will follow which define the status of

the addressed slaves. A command word consists of

a control byte, which defines Co and D/C, plus a data byte

(see Fig.28 and Table 4).

The last control byte is tagged with a cleared MSB, the

continuation bit Co. The control and data bytes are also

acknowledged by all addressed slaves on the bus.

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