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PCF8811U/2DA/1 Fiches technique(PDF) 56 Page - NXP Semiconductors |
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PCF8811U/2DA/1 Fiches technique(HTML) 56 Page - NXP Semiconductors |
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56 / 73 page ![]() 2004 May 17 56 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 22.2 Temperature coefficient selection The second feature is an OTP factory default setting for the temperature coefficient selection (MMTC) in the basic command set. This 3-bit value will be loaded from OTP after leaving the power-save mode or by the refresh command. The idea of this feature is to provide, in the basic command set, the complete set of temperature coefficients without an additional command. In the extended command set the temperature coefficient can be programmed as given in Table 16. 22.3 Seal bit The module maker programming is performed in a special mode: the calibration mode (CALMM). This mode is entered via a special interface command, CALMM. To prevent wrongful programming, a seal bit has been implemented which prevents the device from entering the calibration mode. This seal bit, once programmed, can not be reversed, thus further changes in programmed values are not possible. Applying the programming voltages when not in CALMM mode will have no effect on the programmed values. Table 23 Seal bit definition 22.4 OTP architecture The OTP circuitry in the PCF8811 contains 9 bits of data: 5 for VLCD calibration (MMVOPCAL), 3 for the temperature coefficient default setting in the basic command set MMTC and 1 seal bit. The circuitry for 1-bit is called an OTP slice. Each OTP slice consists of 2 main parts: the OTP cell (a non-volatile memory cell) and the shift register cell (a flip-flop). The OTP cells are only accessible through their shift register cells: on the one hand both reading from and writing to the OTP cells is performed with the shift register cells, on the other hand only the shift register cells are visible to the rest of the circuit. The basic OTP architecture is shown in Fig.48. This OTP architecture allows the following operations: 1. Reading data from the OTP cells. The content of the non-volatile OTP cells is transferred to the shift register where upon it may affect the PCF8811 operation. 2. Writing data to the OTP cells. First, all 9 bits of data are shifted into the shift register via the interface. The content of the shift register is then transferred to the OTP cells (there are some limitations related to storing data in these cells; see Section 22.7). 3. Checking calibration without writing to the OTP cells. Shifting data into the shift register allows the effects on the VLCD voltage to be observed. The reading of data from the OTP cells is initiated by either: • Exit from power-save mode • The ‘Refresh’ command (power control). It should be noted that in both cases the reading operation needs up to 5 ms to complete. The shifting of data into the shift register is performed in the special mode CALMM. In the PCF8811 the CALMM mode is entered by the CALMM command. Once in the CALMM mode the data is shifted into the shift register via the interface at the rate of 1-bit per command. After transmitting the last (9th) bit and exiting the CALMM mode, the serial interface will return to the normal mode and all other commands can be sent. Care should be taken that 9 bits of data (or a multiple of 9) are always transferred before exiting the CALMM mode, otherwise the bits will be in the wrong positions. In the shift register the value of the seal bit is, like the others, always zero at reset. To ensure that the security feature works correctly, the CALMM command is disabled until a refresh has been performed. Once the refresh is completed, the seal bit value in the shift register will be valid and permission to enter the CALMM mode can thus be determined. The 9 bits are shifted into the shift register in a predefined order: first 5 bits of MMVOPCAL[4:0], 3 bits for MMTC[2:0] and lastly the seal bit. The MSB is always first, thus the first bit shifted is MMVOPCAL[4] and the two last bits are MMTC[0] and the seal bit. SEAL BIT ACTION 0 possible to enter calibration mode 1 calibration mode disabled |
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