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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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PCF8811U/2DA/1 Fiches technique(PDF) 47 Page - NXP Semiconductors |
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PCF8811U/2DA/1 Fiches technique(HTML) 47 Page - NXP Semiconductors |
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47 / 73 page  2004 May 17 47 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 19 SERIAL INTERFACE TIMING CHARACTERISTICS VDD1 = 1.8 V to 3.3 V; VSS =0V; VLCD = maximum 9.0 V; Tamb = −40 °C to +85 °C; note 1; unless otherwise specified. Notes 1. All specified timings are based on 20 % and 80 % of VDD. 2. tH5 is the time from the previous SCLK rising edge (irrespective of the state of SCE) to the falling edge of SCE. 3. SDOUT disable time for SPI 3-line or 4-line interface. 4. SDOUT disable time for serial interface 3-line. 5. Maximum values are for fSCLK = 9 MHz. Series resistance includes ITO track + connector resistance + printed-circuit board. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT 3-line and 4-line (SPI and serial interface); see Fig.37 to Fig.40 fSCLK clock frequency 9.00 − MHz Tcyc clock cycle SCLK 111 − ns tPWH1 SCLK pulse width HIGH 45 − ns tPWL1 SCLK pulse width LOW 45 − ns tS2 SCE set-up time 50 − ns tH2 SCE hold time 45 − ns tPWH2 SCE minimum high time 50 − ns tH5 SCE start hold time note 2 50 − ns tS4 SDIN set-up time 50 − ns tH4 SDIN hold time 50 − ns tS3 data/command set-up time 50 − ns tH3 data/command hold time 50 − ns tS1 SDIN set-up time 50 − ns tH1 SDIN hold time 50 − ns t1 SDOUT access time − 50 ns t2 SDOUT disable time note 3 − 50 ns t3 SCE hold time 50 − ns t4 SDOUT disable time note 4 25 100 ns Cb capacitive load for SDO note 5 − 30 pF Rb series resistance for SDO note 5 − 500 Ω |
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